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AD2S1205 Arkusz danych(PDF) 10 Page - Analog Devices |
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AD2S1205 Arkusz danych(HTML) 10 Page - Analog Devices |
10 / 20 page AD2S1205 Rev. A | Page 10 of 20 SIGNAL DEGRADATION DETECTION Degradation of signal (DOS) is detected when either resolver input (Sin or Cos) exceeds the specified DOS Sin/Cos threshold. The AD2S1205 detects this by comparing the monitor signal to a fixed maximum value. In addition, DOS is detected when the amplitudes of the Sin and Cos input signals are mismatched by more than the specified DOS Sin/Cos mismatch. This is identified because the AD2S1205 continuously stores the minimum and maximum magnitude of the monitor signal in internal registers and calculates the difference between these values. DOS is indicated by a logic low on the DOS pin and is not latched when the input signals exceed the maximum input level. When DOS is indicated due to mismatched signals, the output is latched low until a rising edge of SAMPLE resets the stored minimum and maximum values. The DOS condition has priority over the LOT condition, as shown in . DOS is indicated within 33° of the angular output error (worst case). Table 4 LOSS OF POSITION TRACKING DETECTION Loss of tracking (LOT) is detected when • The internal error signal of the AD2S1205 exceeds 5°. • The input signal exceeds the maximum tracking rate. • The internal position (at the position integrator) differs from the external position (at the position register) by more than 5°. LOT is indicated by a logic low on the LOT pin and is not latched. LOT has a 4° hysteresis and is not cleared until the internal error signal or internal/external position mismatch is less than 1°. When the maximum tracking rate is exceeded, LOT is cleared only if the velocity is less than the maximum tracking rate and the internal/external position mismatch is less than 1°. LOT can be indicated for step changes in position (such as after a RESET signal is applied to the AD2S1205), or for accelerations of >~65,000 rps2. It is also useful as a built-in test to indicate that the tracking converter is functioning properly. The LOT condition has lower priority than both the DOS and LOS conditions, as shown in . The LOT and DOS conditions cannot be indicated at the same time. Table 4 Table 4. Fault Detection Decoding Condition DOS Pin LOT Pin Order of Priority Loss of Signal (LOS) 0 0 1 Degradation of Signal (DOS) 0 1 2 Loss of Tracking (LOT) 1 0 3 No Fault 1 1 RESPONDING TO A FAULT CONDITION If a fault condition (LOS, DOS, or LOT) is indicated by the AD2S1205, the output data is presumed to be invalid. Even if a RESET or SAMPLE pulse releases the fault condition and is not immediately followed by another fault, the output data may be corrupted. As discussed previously, there are some fault conditions with inherent latency. If the device fault is cleared, there may be some latency in the resolver’s mechanical position before the fault condition is reindicated. When a fault is indicated, all output pins still provide data, although the data may or may not be valid. The fault condition does not force the parallel, serial, or encoder outputs to a known state. Response to specific fault conditions is a system-level requirement. The fault outputs of the AD2S1205 indicate that the device has sensed a potential problem with either the internal or external signals of the AD2S1205. It is the responsibility of the system designer to implement the appropriate fault-handling schemes within the control hardware and/or algorithm of a given appli- cation based on the indicated fault(s) and the velocity or position data provided by the AD2S1205. FALSE NULL CONDITION Resolver-to-digital converters that employ Type II tracking loops based on the previously stated error equation (see Equation 4 in the Theory of Operation section) can suffer from a condition known as a false null. This condition is caused by a metastable solution to the error equation when θ − ϕ = 180°. The AD2S1205 is not susceptible to this condition because its hysteresis is implemented external to the tracking loop. As a result of the loop architecture chosen for the AD2S1205, the internal error signal constantly has some movement (1 LSB per clock cycle); therefore, in a metastable state, the converter moves to an unstable condition within one clock cycle. This causes the tracking loop to respond to the false null condition as if it were a 180° step change in input position (the response time is the same, as specified in the Dynamic Performance section of Table 1). Therefore, it is impossible to enter the metastable condition after the start-up sequence if the resolver signals are valid. |
Podobny numer części - AD2S1205_15 |
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Podobny opis - AD2S1205_15 |
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