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ADW71205WSTZ-RL Datasheet(Arkusz danych) 4 Page - Analog Devices

Numer części ADW71205WSTZ-RL
Szczegółowy opis  12-Bit RDC with Reference Oscillator
Pobierz  20 Pages
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
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AD2S1205
Rev. A | Page 4 of 20
Parameter
Min
Typ
Max
Unit
Conditions/Comments
Degradation of Signal (DOS)
Sin/Cos Threshold
4.0
4.09
4.2
V p-p
DOS goes low when Sin or Cos exceeds threshold
Angular Accuracy (Worst Case)
33
Degrees
DOS indicated before angular output error exceeds limit
Angular Latency (Worst Case)
66
Degrees
Maximum electrical rotation before DOS is indicated
Time Latency
125
μs
Sin/Cos Mismatch
385
420
mV
DOS latched low when Sin/Cos amplitude mismatch
exceeds threshold
Loss of Tracking (LOT)
Tracking Threshold
5
Degrees
LOT goes low when internal error signal exceeds
threshold; guaranteed by design
Time Latency
1.1
ms
Hysteresis
4
Degrees
Guaranteed by design
VOLTAGE REFERENCE
REFOUT
2.39
2.47
2.52
V
±IOUT = 100 μA
Drift
70
ppm/°C
PSRR
−60
dB
CHARGE-PUMP OUTPUT (CPO)
Frequency
204.8
kHz
Square wave output, CLKIN = 8.192 MHz
Duty Cycle
50
%
POWER SUPPLY
IDD Dynamic
20
mA
ELECTRICAL CHARACTERISTICS
VIL, Voltage Input Low
0.8
V
VIH, Voltage Input High
2.0
V
VOL, Voltage Output Low
0.4
V
+1 mA load
VOH, Voltage Output High
4.0
V
−1 mA load
IIL, Low Level Input Current
(Non-Pull-Up)
−10
+10
μA
SAMPLE, CS, RDVEL, CLKIN, SOE pins
IIL, Low Level Input Current (Pull-Up)
−80
+80
μA
RD, FS1, FS2, RESET pins
IIH, High Level Input Current
−10
+10
μA
IOZH, High Level Three-State Leakage
−10
+10
μA
IOZL, Low Level Three-State Leakage
−10
+10
μA
1 The voltages for Sin, SinLO, Cos, and CosLO relative to AGND must be between 0.2 V and AVDD.




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