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TP7C31BH Arkusz danych(PDF) 6 Page - Intel Corporation |
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TP7C31BH Arkusz danych(HTML) 6 Page - Intel Corporation |
6 / 16 page AUTOMOTIVE 80C31BH80C51BH87C51 Table 2 Status of the External Pins During Idle and Power Down Mode Program ALE PSEN PORT0 PORT1 PORT2 PORT3 Memory Idle Internal 1 1 Data Data Data Data Idle External 1 1 Float Data Address Data Power Down Internal 0 0 Data Data Data Data Power Down External 0 0 Float Data Data Data NOTE For more detailed information on the reduced power modes refer to current Embedded Applications Handbook and Applica- tion Note AP-252 ‘‘Designing with the 80C51BH’’ internal RAM in this event but access to the port pins is not inhibited To eliminate the possibility of an unexpected write to a port pin when Idle is terminat- ed by reset the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory POWER DOWN MODE In the Power Down mode the oscillator is stopped and the instruction that invokes Power Down is the last instruction executed The on-chip RAM and Special Function Registers retain their values until the Power Down mode is terminated The only exit from Power Down is a hardware reset Reset redefines the SFRs but does not change the on-chip RAM The reset should not be activated be- fore VCC is restored to its normal operating level and must be held active long enough to allow the oscilla- tor to restart and stabilize DESIGN CONSIDERATIONS At power on the voltage on VCC and RST must come up at the same time for a proper start-up Before entering the Power Down mode the con- tents of the Carry Bit and B7 must be equal When the Idle mode is terminated by a hardware reset the device normally resumes program exe- cution from where it left off up to two machine cycles before the internal reset algorithm takes control On-chip hardware inhibits access to inter- nal RAM in this event but access to the port pins in not inhibited To eliminate the possibility of an unexpected write when Idle is terminated by re- set the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory An external oscillator may encounter as much as a 100 pF load at XTAL1 when it starts up This is due to interaction between the amplifier and its feedback capacitance Once the external signal meets the VIL and VIH specifications the capaci- tance will not exceed 20 pF For EPROM versions exposure to light when the device is in operation may cause logic errors For this reason it is suggested that an opaque label be placed over the window when the die is ex- posed to ambient light 6 |
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