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SI5435BDC Arkusz danych(PDF) 8 Page - Vishay Siliconix |
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SI5435BDC Arkusz danych(HTML) 8 Page - Vishay Siliconix |
8 / 10 page AN811 Vishay Siliconix www.vishay.com 2 Document Number: 71126 12-Dec-03 Front of Board FIGURE 3. Back of Board vishay.com ChipFETr THERMAL PERFORMANCE Junction-to-Foot Thermal Resistance (the Package Performance) Thermal performance for the 1206-8 ChipFET measured as junction-to-foot thermal resistance is 15_C/W typical, 20_C/W maximum for the single device. The “foot” is the drain lead of the device as it connects with the body. This is identical to the SO-8 package RQjf performance, a feat made possible by shortening the leads to the point where they become only a small part of the total footprint area. Junction-to-Ambient Thermal Resistance (dependent on pcb size) The typical RQja for the single-channel 1206-8 ChipFET is 80_C/W steady state, compared with 68_C/W for the SO-8. Maximum ratings are 95_C/W for the 1206-8 versus 80_C/W for the SO-8. Testing To aid comparison further, Figure 4 illustrates ChipFET 1206-8 thermal performance on two different board sizes and three different pad patterns. The results display the thermal performance out to steady state and produce a graphic account of how an increased copper pad area for the drain connections can enhance thermal performance. The measured steady state values of RQja for the single 1206-8 ChipFET are : 1) Minimum recommended pad pattern (see Figure 2) on the evaluation board size of 0.5 in x 0.6 in. 156_C/W 2) The evaluation board with the pad pattern described on Figure 3. 111_C/W 3) Industry standard 1” square pcb with maximum copper both sides. 78_C/W The results show that a major reduction can be made in the thermal resistance by increasing the copper drain area. In this example, a 45_C/W reduction was achieved without having to increase the size of the board. If increasing board size is an option, a further 33_C/W reduction was obtained by maximizing the copper from the drain on the larger 1” square pcb. Time (Secs) FIGURE 4. Single 1206−8 ChipFET 0 1 160 40 80 100 1000 120 10 10-1 10-2 10-3 10-4 10-5 1” Square PCB Single EVB Min. Footprint SUMMARY The thermal results for the single-channel 1206-8 ChipFET package display similar power dissipation performance to the SO-8 with a footprint reduction of 80%. Careful design of the package has allowed for this performance to be achieved. The short leads allow the die size to be maximized and thermal resistance to be reduced within the confines of the TSOP-6 body size. ASSOCIATED DOCUMENT 1206-8 ChipFET Dual Thermal performance, AN812 (http://www.vishay.com/doc?71127). |
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