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AD5662 Arkusz danych(PDF) 7 Page - Analog Devices |
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AD5662 Arkusz danych(HTML) 7 Page - Analog Devices |
7 / 24 page AD5662 Rev. A | Page 7 of 24 PIN CONFIGURATION AND FUNCTION DESCRIPTION VDD 1 VREF 2 VFB 3 VOUT 4 GND 8 DIN 7 SCLK 6 SYNC 5 AD5662 TOP VIEW (Not to Scale) Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Function 1 VDD Power Supply Input. These parts can be operated from 2.7 V to 5.5 V. VDD should be decoupled to GND. 2 VREF Reference Voltage Input. 3 VFB Feedback Connection for the Output Amplifier. VFB should be connected to VOUT for normal operation. 4 VOUT Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation. 5 SYNC Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register, and data is transferred in on the falling edges of the following clocks. The DAC is updated following the 24th clock cycle unless SYNC is taken high before this edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. 6 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 30 MHz. 7 DIN Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. 8 GND Ground Reference Point for All Circuitry on the Part. |
Podobny numer części - AD5662_15 |
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Podobny opis - AD5662_15 |
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