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AD5644R Arkusz danych(PDF) 9 Page - Analog Devices

Numer części AD5644R
Szczegółowy opis  Quad, 12-/14-/16-Bit nanoDACs with 5 ppm/C On-Chip Reference
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
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AD5644R Arkusz danych(HTML) 9 Page - Analog Devices

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Data Sheet
AD5624R/AD5644R/AD5664R
Rev. C | Page 9 of 28
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 3. 10-Lead LFCSP and 10-Lead MSOP Pin Configuration
Figure 4. 12-Ball WLCSP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
LFCSP
MSOP
WLCSP
Mnemonic
Description
1
1
A3
VOUTA
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
2
2
B3
VOUTB
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
3
3
A2, B2,
C2
GND
Ground Reference Point for all Circuitry on the Part.
4
4
C3
VOUTC
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
5
5
D3
VOUTD
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
6
6
D2
SYNC
Active Low Control Input. This is the frame synchronization signal for the input data.
When SYNC goes low, it powers on the SCLK and DIN buffers and enables the input shift
register. Data is transferred in on the falling edges of the next 24 clocks. If SYNC is taken high
before the 24th falling edge, the rising edge of SYNC acts as an interrupt and the write
sequence is ignored by the device.
7
7
D1
SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial
clock input. Data can be transferred at rates up to 50 MHz.
8
8
C1
DIN
Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the
falling edge of the serial clock input.
9
9
B1
VDD
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be
decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
10
10
A1
VREFIN/VREFOUT
The AD5624R/AD5644R/AD5664R have a common pin for reference input and reference
output. When using the internal reference, this is the reference output pin. When using an
external reference, this is the reference input pin. The default for this pin is as a reference input.
N/A
N/A
EPAD
Exposed Pad. The exposed pad must be tied to GND on the LFCSP package.
1
VOUTA
10
VREFIN/VREFOUT
2
VOUTB
9
VDD
3
GND
8
DIN
4
VOUTC
7
SCLK
5
VOUTD
6
SYNC
AD5624R/
AD5644R/
AD5664R
TOP VIEW
(Not to Scale)
EXPOSED PAD TIED TO
GND ON LFCSP PACKAGE
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
GND VOUTA
VDD
GND VOUTB
DIN
GND VOUTC
SCLK SYNC VOUTD
1
A
B
C
D
2
3
BALL A1
INDICATOR
VREFIN/
VREFOUT


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