AD7366-5/AD7367-5

Rev. B | Page 7 of 28

TIMING SPECIFICATIONS

Table 4.

Parameter

Unit

Test Conditions/Comments

Conversion time, internal clock. CONVST falling edge to BUSY falling edge.

1.25

μs max

For the AD7367-5.

1.25

μs max

For the AD7366-5.

10

kHz min

Frequency of serial read clock.

20

MHz max

50

ns min

Minimum quiet time required between the end of serial read and the start of the next

conversion.

10

ns min

Minimum CONVST low pulse.

40

ns min

CONVST falling edge to BUSY rising edge.

0

ns min

10

ns max

t52

20

ns max

Data access time after SCLK falling edge.

7

ns min

SCLK to data valid hold time.

ns min

SCLK low pulse width.

ns min

SCLK high pulse width.

10

ns max

70

μs max

Power up time from shutdown mode; time required between CONVST rising edge and

CONVST falling edge.

All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. See the

Terminology section and Figure 25.