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AD7414ARTZ-3REEL Arkusz danych(PDF) 4 Page - Analog Devices |
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AD7414ARTZ-3REEL Arkusz danych(HTML) 4 Page - Analog Devices |
4 / 20 page AD7414/AD7415 Rev. F | Page 4 of 20 Parameter A Version Unit Test Conditions/Comments AC ELECTRICAL CHARACTERISTICS8, 9 Serial Clock Period, t1 2.5 μs min See Figure 2 Data In Setup Time to SCL High, t2 50 ns min See Figure 2 Data Out Stable after SCL Low, t3 0 ns min See Figure 2 SDA Low Setup Time to SCL Low (Start Condition), t4 50 ns min See Figure 2 SDA High Hold Time after SCL High (Stop Condition), t5 50 ns min See Figure 2 SDA and SCL Fall Time, t6 90 ns max See Figure 2 Data Hold Time, t7 35 ns min See Figure 2 Power-Up Time 4 μs typ 1 Accuracy specifications apply only to voltages listed under Test Conditions. See Temperature Accuracy vs. Supply section for typical accuracy performance over the full VDD supply range. 2 100% production tested at 40°C to these limits. 3 These current values can be used to determine average power consumption at different one-shot conversion rates. Average power consumption at the automatic conversion rate of 1.25 kHz is 940 μW. 4 This peak supply current is required for 29 μs (the conversion time plus power-up time) out of every 800 μs (the conversion rate). 5 These current values are derived by not issuing a stop condition at the end of a write or read, thus preventing the part from going into a conversion. 6 The current is derived assuming a 400 kHz serial clock being active continuously. 7 On power-up, the initial input current, IIN, on the AS pin is typically 50 μA. 8 The SDA and SCL timing is measured with the input filters turned on so as to meet the fast mode I2C specification. Switching off the input filters improves the transfer rate but has a negative effect on the EMC behavior of the part. 9 Guaranteed by design. Not tested in production. SCL SDA DATA IN SDA DATA OUT t1 t2 t7 t3 t4 t5 t6 Figure 2. Diagram for Serial Bus Timing |
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