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AD7667 Arkusz danych(PDF) 8 Page - Analog Devices

Numer części AD7667
Szczegółowy opis  Unipolar ADC with Reference
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Strona internetowa  http://www.analog.com
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AD7667 Arkusz danych(HTML) 8 Page - Analog Devices

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AD7667
Rev. 0 | Page 8 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44
39 38 37
43 42 41 40
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
AGND
CNVST
PD
RESET
CS
RD
DGND
AGND
AVDD
NC
BYTESWAP
OB/2C
WARP
IMPULSE
NC = NO CONNECT
SER/PAR
D0
D1
BUSY
D15
D14
D13
AD7667
D3/DIVSCLK1
D12
D2/DIVSCLK0
Figure 4. 48-Lead LQFP (ST-48) and 48-Lead LFCSP (CP-48)
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
1, 36, 41, 42
AGND
P
Analog Power Ground Pin.
2, 44
AVDD
P
Input Analog Power Pin. Nominally 5 V.
3, 40
NC
No Connect.
6
WARP
DI
Mode Selection. When this pin is HIGH and the IMPULSE pin is LOW, this input selects the fastest
mode, the maximum throughput is achievable, and a minimum conversion rate must be applied in
order to guarantee full specified accuracy. When LOW, full accuracy is maintained independent of the
minimum conversion rate.
7
IMPULSE
DI
Mode Selection. When IMPULSE is HIGH and WARP is LOW, this input selects a reduced power mode.
In this mode, the power dissipation is approximately proportional to the sampling rate.
4
BYTESWAP
DI
Parallel Mode Selection (8-/16-bit). When LOW, the LSB is output on D[7:0] and the MSB is output on
D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0].
5
OB/2C
DI
Straight Binary/Binary Twos Complement. When OB/2C is HIGH, the digital output is straight binary;
when LOW, the MSB is inverted, resulting in a twos complement output from its internal shift register.
8
SER/PAR
DI
Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the serial interface
mode is selected and some bits of the DATA bus are used as a serial port.
9, 10
D[0:1]
DO
Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs are in high
impedance.
11, 12
D[2:3]or
DIVSCLK[0:1]
DI/O
When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus.
When SER/PAR is HIGH, EXT/INT is LOW, and RDC/SDIN is LOW (serial master read after convert), these
inputs, part of the serial port, are used to slow down, if desired, the internal serial clock that clocks the
data output. In other serial modes, these pins are not used.
13
D4 or
EXT/INT
DI/O
When SER/PAR is LOW, this output is used as Bit 4 of the parallel port data output bus.
When SER/PAR is HIGH, this input, part of the serial port, is used as a digital select input for choosing
the internal data clock or an external data clock. With EXT/INT tied LOW, the internal clock is selected
on the SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to an external clock
signal connected to the SCLK input.
14
D5 or
INVSYNC
DI/O
When SER/PAR is LOW, this output is used as Bit 5 of the parallel port data output bus.
When SER/PAR is HIGH, this input, part of the serial port, is used to select the active state of the SYNC
signal. It is active in both master and slave modes. When LOW, SYNC is active HIGH. When HIGH, SYNC
is active LOW.
15
D6 or
INVSCLK
DI/O
When SER/PAR is LOW, this output is used as Bit 6 of the parallel port data output bus.
When SER/PAR is HIGH, this input, part of the serial port, is used to invert the SCLK signal. It is active in
both master and slave modes.


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