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AD8339 Arkusz danych(PDF) 4 Page - Analog Devices |
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AD8339 Arkusz danych(HTML) 4 Page - Analog Devices |
4 / 36 page AD8339 Data Sheet Rev. B | Page 4 of 36 Parameter Test Conditions/Comments Min Typ Max Unit LOGIC INTERFACES Pin SDI, Pin CSB, Pin SCLK, Pin RSET Logic Level High 1.5 V Logic Level Low 0.9 V Pin RSTS Logic Level High 1.8 V Logic Level Low 1.2 V Bias Current Logic high (pulled to 5 V) 0.5 μA Logic low (pulled to GND) 0 μA Input Resistance 4 MΩ LO Divider RSET Setup Time RSET rising or falling edge to 4LOP or 4LON (differential) rising edge 5 ns LO Divider RSET High Pulse Width 20 ns LO Divider RSET Response Time 200 ns Phase Response Time Measured from CSB going high 5 μs Enable Response Time Measured from CSB going high (with 0.1 μF capacitor on Pin LODC); no channel enabled 12 15 μs At least one channel enabled 500 ns Output Pin SDO loaded with 5 pF and next SDI input Logic Level High 1.7 1.9 V Logic Level Low 0.2 0.5 V SPI TIMING CHARACTERISTICS Pin SDI, Pin SDO, Pin CSB, Pin SCLK, Pin RSTS SCLK Frequency fCLK 10 MHz CSB Fall to SCLK Setup Time t1 0 ns SCLK High Pulse Width t2 10 ns SCLK Low Pulse Width t3 10 ns Data Access Time (SDO) After SCLK Rising Edge t4 100 ns Data Setup Time Before SCLK Rising Edge t5 2 ns Data Hold Time After SCLK Rising Edge t6 2 ns SCLK Rise to CSB Rise Hold Time t7 15 ns CSB Rise to SCLK Rise Hold Time t8 0 ns POWER SUPPLY Pin VPOS, Pin VNEG Supply Voltage ±4.5 ±5.0 ±5.5 V Current VPOS, all phase bits = 0 35 mA VNEG, all phase bits = 0 −18 mA Over Temperature, −40°C < TA < +85°C VPOS, all phase bits = 0 33 36 mA VNEG, all phase bits = 0 −19 −17 mA Quiescent Power Per channel, all phase bits = 0 66 mW Per channel maximum (depends on phase bits) 88 mW Disable Current All channels disabled; SPI stays on 2.75 mA PSRR VPOS to Ix/Qx outputs, @ 10 kHz −85 dB VNEG to Ix/Qx outputs, @ 10 kHz −85 dB |
Podobny numer części - AD8339_15 |
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Podobny opis - AD8339_15 |
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