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AD9389A Arkusz danych(PDF) 5 Page - Analog Devices

Numer części AD9389A
Szczegółowy opis  High Performance HDMI/DVI Transmitter
Download  12 Pages
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
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AD9389A Arkusz danych(HTML) 5 Page - Analog Devices

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AD9389A
Rev. 0 | Page 5 of 12
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DVDD
D0
DE
HSYNC
VSYNC
CLK
S/PDIF
MCLK
I2S0
I2S1
I2S2
I2S3
SCLK
LRCLK
PVDD
PVDD
NC = NO CONNECT
DVDD
D15
D16
D17
D18
D19
D20
D21
D22
D23
NC
NC
SDA
SCL
DDCSDA
DDCSCL
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AD9389A
TOP VIEW
(Not to Scale)
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
2, 39 to 47,
50 to 63
D[23:0]
I
Video Data Input. Digital input in RGB or YCbCr format. Supports CMOS logic levels from 1.8 V to 3.3 V.
6
CLK
I
Video Clock Input. Supports CMOS logic levels from 1.8 V to 3.3 V.
3
DE
I
Data Enable Bit for Digital Video. Supports CMOS logic levels from 1.8 V to 3.3 V.
4
HSYNC
I
Horizontal SYNC Input. Supports CMOS logic levels from 1.8 V to 3.3 V.
5
VSYNC
I
Vertical SYNC Input. Supports CMOS logic levels from 1.8 V to 3.3 V.
18
EXT_SW
I
Sets internal reference currents. Place 887 Ω resistor (1% tolerance) between this pin and ground.
20
HPD
I
Hot Plug Detect Signal. This indicates to the interface whether the receiver is connected. 1.8 V to
5.0 V CMOS logic level.
7
S/PDIF
I
S/PDIF (Sony/Philips Digital Interface) Audio Input. This is the audio input from a Sony/Philips
digital interface. Supports CMOS logic levels from 1.8 V to 3.3 V.
8
MCLK
I
Audio Reference Clock. 128 × N × fS with N = 1, 2, 3, or 4. Set to 128 × sampling frequency (fS),
256 × fS, 384 × fS, or 512 × fS. 1.8 V to 3.3 V CMOS logic level.
9 to 12
I2S[3:0]
I
I2S Audio Data Inputs. These represent the eight channels of audio (two per input) available
through I2S. Supports CMOS logic levels from 1.8 V to 3.3 V.
13
SCLK
I
I2S Audio Clock. Supports CMOS logic levels from 1.8 V to 3.3 V.
14
LRCLK
I
Left/Right Channel Selection. Supports CMOS logic levels from 1.8 V to 3.3 V.
26
PD/A0
I
Power-Down Control and I2C Address Selection. The I2C address and the PD polarity are set by the
PD/A0 pin state when the supplies are applied to the AD9389A. 1.8 V to 3.3 V CMOS logic level.
21, 22
TxC−/TxC+
O
Differential Clock Output. Differential clock output at pixel clock rate; transition minimized
differential signaling (TMDS) logic level.
31, 32
Tx2−/Tx2+
O
Differential Output Channel 2. Differential output of the red data at 10 × the pixel clock rate;
TMDS logic level.
27, 28
Tx1−/Tx1+
O
Differential Output Channel 1. Differential output of the green data at 10 × the pixel clock rate;
TMDS logic level.
24, 25
Tx0−/Tx0+
O
Differential Output Channel 0. Differential output of the blue data at 10 × the pixel clock rate;
TMDS logic level.
32
INT
O
Interrupt. CMOS logic level. A 2 kΩ pull up resistor to interrupt the microcontroller IO supply is
recommended.
19, 23, 29
AVDD
P
1.8 V Power Supply for TMDS Outputs.


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