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AD9751 Arkusz danych(PDF) 1 Page - Analog Devices

Numer części AD9751
Szczegółowy opis  10-Bit, 300 MSPS
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Strona internetowa  http://www.analog.com
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AD9751 Arkusz danych(HTML) 1 Page - Analog Devices

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REV. C
a
AD9751*
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
10-Bit, 300 MSPS
High Speed TxDAC+® D/A Converter
FUNCTIONAL BLOCK DIAGRAM
AVDD
ACOM
REFIO
FSADJ
PORT1
IOUTA
IOUTB
AD9751
DVDD
DCOM
LATCH
LATCH
CLK+
CLK–
CLKVDD
PLLVDD
CLKCOM
RESET LPF DIV0 DIV1 PLLLOCK
PLL
CLOCK
MULTIPLIER
DAC
REFERENCE
MUX
PORT2
PRODUCT DESCRIPTION
The AD9751 is a dual muxed port, ultrahigh speed, single-
channel, 10-bit CMOS DAC. It integrates a high quality 10-bit
TxDAC+ core, a voltage reference, and digital interface circuitry
into a small 48-lead LQFP package. The AD9751 offers excep-
tional ac and dc performance while supporting update rates up
to 300 MSPS.
The AD9751 has been optimized for ultrahigh speed applica-
tions up to 300 MSPS where data rates exceed those possible on
a single data interface port DAC. The digital interface consists
of two buffered latches as well as control logic. These latches
can be time multiplexed to the high speed DAC in several ways.
This PLL drives the DAC latch at twice the speed of the exter-
nally applied clock and is able to interleave the data from the
two input channels. The resulting output data rate is twice that
of the two input channels. With the PLL disabled, an external
2
× clock may be supplied and divided by two internally.
The CLK inputs (CLK+/CLK–) can be driven either differen-
tially or single-ended, with a signal swing as low as 1 V p-p.
FEATURES
10-Bit Dual Muxed Port DAC
300 MSPS Output Update Rate
Excellent SFDR and IMD Performance
SFDR to Nyquist @ 25 MHz Output: 64 dB
Internal Clock Doubling PLL
Differential or Single-Ended Clock Input
On-Chip 1.2 V Reference
Single 3.3 V Supply Operation
Power Dissipation: 155 mW @ 3.3 V
48-Lead LQFP
APPLICATIONS
Communications: LMDS, LMCS, MMDS
Base Stations
Digital Synthesis
QAM and OFDM
The DAC utilizes a segmented current source architecture com-
bined with a proprietary switching technique to reduce glitch
energy and maximize dynamic accuracy. Differential current
outputs support single-ended or differential applications. The
differential outputs each provide a nominal full-scale current
from 2 mA to 20 mA.
The AD9751 is manufactured on an advanced low cost 0.35
µm
CMOS process. It operates from a single supply of 3.0 V to 3.6 V
and consumes 155 mW of power.
PRODUCT HIGHLIGHTS
1. The AD9751 is a member of a pin compatible family of high
speed TxDAC+s, providing 10-, 12-, and 14-bit resolution.
2. Ultrahigh Speed 300 MSPS Conversion Rate.
3. Dual 10-Bit Latched, Multiplexed Input Ports. The AD9751
features a flexible digital interface allowing high speed data
conversion through either a single or dual port input.
4. Low Power. Complete CMOS DAC function operates on
155 mW from a 3.0 V to 3.6 V single supply. The DAC full-
scale current can be reduced for lower power operation.
5. On-Chip Voltage Reference. The AD9751 includes a 1.20 V
temperature compensated band gap voltage reference.
*Protected by U.S. Patent numbers 5450084, 5568145, 5689257, and 5703519.


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