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AD9782 Arkusz danych(PDF) 8 Page - Analog Devices

Numer części AD9782
Szczegółowy opis  12-Bit, 200 MSPS/500 MSPS TxDAC
Download  52 Pages
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
Logo AD - Analog Devices

AD9782 Arkusz danych(HTML) 8 Page - Analog Devices

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AD9782
Preliminary Technical Data
Rev. PrC | Page 8 of 52
ANALOG
Table 5. Analog Pin Function Descriptions
Pin No.
Mnemonic
Direction
Description
59
REFIO
A
Reference.
60
FSADJ
A
Full-Scale Adjust.
70, 71
IOUTB, IOUTA
A
Differential DAC Output Currents.
61
DNC
Do not connect.
62, 79
ADVDD
Analog Domain Digital Content 2.5 V.
63, 78
ADGND
Analog Domain Digital Content 0 V.
64, 77
ACVDD
Analog Domain Clock Content 2.5 V.
65, 76
ACGND
Analog Domain Clock Content 0 V.
66, 75
AVDD2
Analog Domain Clock Switching 3.3 V.
67, 74
AGND2
Analog Domain Switching 0 V.
68, 73
AVDD1
Analog Domain Quiet 3.3 V.
69, 72
AGND1
Analog Domain Quiet 0 V.
DATA
Table 6. Data Pin Function Descriptions
Pin No.
Mnemonic
Direction
Description
Input Data Port One.
ONEPORT
02h[6]
Mode
0
Latched Data Routed for 1 Channel Processing.
10–15, 18–24,
27–29
P1B15–P1B0
I
1
Latched Data Demultiplexed by IQSEL and Routed for Interleaved
I/Q Processing.
ONEPORT
02h[6]
IQPOL
02h[1]
IQSEL/
P2B15
Mode (IQPOL == 0)
0
X
X
Latched data routed to Q channel bit 15(MSB)
processing.
1
0
0
Latched data on data port one routed to Q
channel processing.
1
0
1
Latched data on data port one routed to I
channel processing.
1
1
0
Latched data on data port one routed to I
channel processing.
32
IQSEL/P2B15
I
1
1
1
Latched data on data port one routed to Q
channel processing.
ONEPORT
02h[6]
0
Latched data routed for Q channel Bit 14 processing.
33
ONEPORTCLK/P2B14
I/O
1
Pin configured for output of clock at twice the channel data route.
34, 37–43,
46–51
P2B13–P2B0
I
Input Data Port Two Bits 13–0.
30
DRVDD
Digital Output Pin Supply, 2.5 V or 3.3 V.
9, 17, 26,
36, 44, 52
DVDD
Digital Domain 2.5 V.
8, 16, 25,
35, 45, 53
DGND
Digital Domain 0 V.


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