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AD73411 Arkusz danych(PDF) 10 Page - Analog Devices |
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AD73411 Arkusz danych(HTML) 10 Page - Analog Devices |
10 / 36 page REV. 0 AD73411 –10– AD73411 AGND1 AGND2 DGND DVDD AVDD2 AVDD1 VINP VINN VOUTP VOUTN REFCAP REFOUT SDI SDIFS SCLK SDO SDOFS SE MCLK RESET 1-BIT DAC REFERENCE SERIAL I/O PORT INTERPOLATOR DECIMATOR SWITCHED- CAPACITOR LOW-PASS FILTER CONTINUOUS TIME LOW-PASS FILTER +6/–15dB PGA 0/38dB PGA ANALOG SIGMA-DELTA MODULATOR DIGITAL SIGMA-DELTA MODULATOR ANALOG LOOPBACK/ SINGLE-ENDED ENABLE Figure 2. Functional Block Diagram of Analog Front End Section The AFE is configured as a single I/O channel (similar to that of the discrete AD73311L; refer to the AD73311L data sheet for more details) having a 16-bit sigma-delta-based ADC and DAC. Both ADC and DAC share a common reference whose nominal value is 1.2 V. Figure 2 shows a block diagram of the AFE sec- tion of the AD73411. It shows an ADC and DAC as well as a common reference. Communication to both channels is handled by the SPORT2 block which interfaces to either SPORT0 or SPORT1 of the DSP section. The I/O channel features fully differential inputs and outputs. The input section allows direct connection to the internal Pro- grammable Gain Amplifier at the input of the sigma-delta ADC section. The input section also features programmable differ- ential channel inversion and configuration of the differential input as two separate single-ended inputs. The ADC features a second order sigma-delta modulator which samples at MCLK/8. Its bitstream output is filtered and decimated by a Sinc-cubed decimator to provide a sample rate selectable from 64 kHz, 32 kHz, 16 kHz or 8 kHz (based on an MCLK of 16.384 MHz). The DAC channel features a Sinc-cubed interpolator which increases the sample rate from the selected rate to the digital sigma-delta modulator rate of MCLK/8. The digital sigma-delta modulator’s output bitstream is fed to a single-bit DAC whose output is reconstructed/filtered by two stages of low-pass filtering (switched capacitor and continuous time) before being applied to the differential output driver. FUNCTIONAL DESCRIPTION Encoder Channel The encoder channel consists of an input configuration block, a switched capacitor PGA and a sigma-delta analog-to-digital converter (ADC). An on-board digital filter, which forms part of the sigma-delta ADC, also performs critical system-level filtering. Due to the high level of oversampling, the input anti- alias requirements are reduced such that a simple single pole RC stage is sufficient to give adequate attenuation in the band of interest. Input Configuration Block The input configuration block consists of a multiplexing arrange- ment that allows selection of various input configurations. This includes ADC input selection from either the VINP, VINN pins or from the DAC output via the Analog Loop-Back (ALB) arrangement. Differential inputs can be inverted and it is also possible to use the device in single-ended mode, which allows the option of using the VINP, VINN pins as two separate single-ended inputs, either of which can be selected under soft- ware control. Programmable Gain Amplifier The encoder section’s analog front end comprises a switched capacitor PGA that also forms part of the sigma-delta modulator. The SC sampling frequency is DMCLK/8. The PGA, whose programmable gain settings are shown in Table I, may be used to increase the signal level applied to the ADC from low output sources such as microphones, and can be used to avoid placing external amplifiers in the circuit. The input signal level to the sigma-delta modulator should not exceed the maximum input voltage permitted. The PGA gain is set by bits IGS0, IGS1 and IGS2 (CRD:0–2) in Control Register D. Table I. PGA Settings for the Encoder Channel IGS2 IGS1 IGS0 Gain (dB) 00 0 0 00 1 6 01 0 12 01 1 18 10 0 20 10 1 26 11 0 32 11 1 38 ADC The ADC consists of an analog sigma-delta modulator and a digital antialiasing decimation filter. The sigma-delta modu- lator noise-shapes the signal and produces 1-bit samples at a DMCLK/8 rate. This bitstream, representing the analog input signal, is input to the antialiasing decimation filter. The decima- tion filter reduces the sample rate and increases the resolution. |
Podobny numer części - AD73411_15 |
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Podobny opis - AD73411_15 |
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