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ADC912A Arkusz danych(PDF) 5 Page - Analog Devices

Numer części ADC912A
Szczegółowy opis  CMOS Microprocessor-Compatible 12-Bit A/D Converter
Download  16 Pages
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
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ADC912A Arkusz danych(HTML) 5 Page - Analog Devices

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REV. B
ADC912A
–5–
WAFER TEST LIMITS
ADC912AG
Parameter
Symbol
Conditions
Limit
Unit
Integral Nonlinearity
INL
±1
LSB max
Differential Nonlinearity
DNL
±1
LSB max
Offset Error
VZSE
Guaranteed by Design
±8
LSB max
Gain Error
GFSE
±8
LSB max
Analog Input Resistance
RAIN
4/6
k
Ω min/max
Logic Input High Voltage
VINH
CS, RD, HBEN
2.4
V min
Logic Input Low Voltage
VINL
CS, RD, HBEN
0.8
V max
Logic Input Current
IIN
CS, RD, HBEN
±1
µA max
Logic Output High Voltage
VOH
ISOURCE = 0.2 mA
4
V min
Logic Output Low Voltage
VOL
ISINK = 1.6 mA
0.4
V max
Positive Supply Current
IDD
VDD = +5 V, CS = RD = VDD, AIN = +10 V
7
mA max
Negative Supply Current
ISS
VSS = –12 V, CS = RD = VDD, AIN = +10 V
5
mA max
NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
(@ VDD = +5 V, VSS = –12 V or –15 V, VREF = –5 V, AIN = 0 V to 10 V, and TA = 25 C, unless otherwise noted.)
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
NC
NC
NC
NC
NC
NC
NC
C1
C2
C1
C2
+
+
C1
C2
C1
C2
+
+
10V
–5V
+5V
–15V
R
R
R
R
R
R
R
R = 10
C1 = 0.01 F
C2 = 4.7 F
NC = NO CONNECT
POWER SUPPLY SEQUENCE:
+5V, –15V, –5V, +10V
ADC912A
TOP VIEW
(Not to Scale)
Figure 9. Burn-In Circuit


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