ADF4001BRUZ datasheet(8/17 Pages) AD

Numer części	ADF4001BRUZ

Szczegółowy opis	200 MHz Clock Generator PLL

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REV.

ADF4001

–8–

Table III. Reference Counter Latch Map

LDP

OPERATION

0THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN

15ns MUST OCCUR BEFORE LOCK DETECT IS SET.

1FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN

15ns MUST OCCUR BEFORE LOCK DETECT IS SET.

ABP2

ABP1

ANTIBACKLASH PULSE WIDTH

00

2.9ns

01

1.3ns

10

6.0ns

11

2.9ns

R14

R13

R12

..........

R3

R2

R1

DIVIDE RATIO

000

..........

0011

000

..........

0102

000

..........

0113

000

..........

1004

...

..........

....

...

..........

....

...

..........

....

111

..........

100

16380

111

..........

101

16381

111

..........

110

16382

111

..........

111

16383

TEST MODE BITS SHOULD

BE SET TO 00 FOR NORMAL

OPERATION

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

C2 (0) C1 (0)

R1

R2

R3

R4

R5

R7

R14

ABP1

T2

LDP

R13

R6

CONTROL

BITS

ABP2

T1

DB21

R12

R11

R10

DB22

DB23

R8

R9

RESERVED

TEST

MODE

BITS

ANTI-

BACKLASH

WIDTH

14-BIT REFERENCE COUNTER

XX

X

X = DON’T CARE

B

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ADF4001BRUZ Arkusz danych(PDF) 8 Page - Analog Devices

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