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ADM8617 Arkusz danych(PDF) 8 Page - Analog Devices |
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ADM8617 Arkusz danych(HTML) 8 Page - Analog Devices |
8 / 12 page ADM8616/ADM8617 Rev. B | Page 8 of 12 CIRCUIT DESCRIPTION The ADM8616/ADM8617 provide microprocessor supply voltage supervision by controlling the microprocessors RESET input. Code execution errors are avoided during power-up, power-down, and brownout conditions by asserting a RESET signal when the supply voltage is below a preset threshold and by allowing supply voltage stabilization with a fixed timeout RESET after the supply voltage rises above the threshold. In addition, problems with microprocessor code execution can be monitored and corrected with a watchdog timer. By including watchdog strobe instructions in microprocessor code, a watch- dog timer can detect if the microprocessor code breaks down or becomes stuck in an infinite loop. If this happens, the watchdog timer asserts a RESET pulse that restarts the microprocessor in a known state. RESET OUTPUT The ADM8616 features an active-low, push-pull RESET output, while the ADM8617 features an active-low, open-drain RESET output. The RESET signal is guaranteed to be logic low and logic high, respectively, for VCC down to 1 V. The RESET output is asserted when VCC is below the RESET threshold (VTH), or when WDI is not serviced within the watchdog timeout period (tWD). RESET remains asserted for the duration of the RESET active timeout period (tRP) after VCC rises above the RESET threshold or after the watchdog timer times out. Figure 11 illustrates the behavior of the RESET outputs. VCC 1V VCC 0V VTH VTH 0V VCC RESET tRD tRP Figure 11. RESET Timing Diagram WATCHDOG INPUT The ADM8616/ADM8617 feature a watchdog timer that monitors microprocessor activity. A timer circuit is cleared with every low-to-high or high-to-low logic transition on the watch- dog input pin (WDI), which detects pulses as short as 50 ns. If the timer counts through the preset watchdog timeout period (tWD), RESET is asserted. The microprocessor is required to toggle the WDI pin to avoid being reset. Failure of the micro- processor to toggle WDI within the timeout period, therefore, indicates a code execution error, and the RESET pulse generated restarts the microprocessor in a known state. In addition to logic transitions on WDI, the watchdog timer is also cleared by a RESET assertion due to an undervoltage condition on VCC. When RESET is asserted, the watchdog timer is cleared and does not begin counting again until RESET deas- serts. The watchdog timer can be disabled by leaving WDI floating or by three-stating the WDI driver. VCC 1V VCC 0V VCC 0V VTH 0V VCC WDI RESET tRP tRD tWD Figure 12. Watchdog Timing Diagram |
Podobny numer części - ADM8617_15 |
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Podobny opis - ADM8617_15 |
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