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ADN2892 Arkusz danych(PDF) 10 Page - Analog Devices |
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ADN2892 Arkusz danych(HTML) 10 Page - Analog Devices |
10 / 16 page ADN2892 Data Sheet THEORY OF OPERATION LIMITING AMPLIFIER Input Buffer The ADN2892 limiting amplifier provides differential inputs (PIN/NIN), each with a single-ended, on-chip 50 Ω termination. The amplifier can accept either dc-coupled or ac-coupled signals; however, an ac-coupled signal is recommended. Using a dc-coupled signal, the amplifier needs a nominal VCC − 0.7 V common-mode voltage and ±0.5 V headroom. If the input common-mode voltage is 2.4 V, the available headroom is reduced down to ±0.3 V. The ADN2892 limiting amplifier is a high gain device. It is susceptible to dc offsets in the signal path. The pulse width distortion presented in the NRZ data or a distortion generated by the TIA may appear as dc offset or a corrupted signal to the ADN2892 inputs. An internal offset correction loop can compensate for certain levels of offset. CML Output Buffer The ADN2892 provides differential CML outputs, OUTP and OUTN. Each output has an internal 50 Ω termination to VCC. LOSS-OF-SIGNAL (LOS) DETECTOR The on-chip LOS circuit drives LOS to logic high when the input signal level falls below a user-programmable threshold. The threshold level can be set anywhere from 3.5 mV p-p to 35 mV p-p typical by a resistor connected between the THRADJ pin and VEE. See Figure 6 and Figure 7 for the LOS threshold vs. THRADJ. The ADN2892 LOS circuit has an electrical hysteresis greater than 2.5 dB to prevent chatter at the LOS signal. The LOS output is an open-collector output that must be pulled up externally with a 4.7 kΩ to 10 kΩ resistor. RECEIVED SIGNAL STRENGTH INDICATOR (RSSI) The ADN2892 has an on-chip, RSSI circuit. By monitoring the current supplied to the photodiode, the RSSI circuit provides an accurate, average power measurement. The output of the RSSI is a current that is directly proportional to the average amount of PIN photodiode current. Placing a resistor between the RSSI_OUT pin and GND converts the current to a GND referenced voltage. This function eliminates the need for external RSSI circuitry for SFF-8472-compliant optical receivers. For more information, see Figure 12 to Figure 16. Connect the PD_VCC, PD_CATHODE, and RSSI_OUT pins to AVCC to disable the RSSI feature. SQUELCH MODE Driving the SQUELCH input to logic high disables the limiting amplifier outputs. Using LOS output to drive the SQUELCH input, the limiting amplifier outputs stop toggling anytime a signal input level to the limiting amplifier drops below the programmed LOS threshold. The SQUELCH pin has a 100 kΩ, internal pull-down resistor. BW_SEL (BANDWIDTH SELECTION) MODE Driving the BW_SEL input signal to logic high, the amplifier provides a 3.8 GHz bandwidth. Driving the BW_SEL input signal to logic low, the amplifier accepts input signals through a 1.5 GHz, 2-pole, low-pass filter that improves receiving sensitivity. The low-pass filter reduces the possible relaxation oscillation of low speed, low cost laser source by limiting the input signal bandwidth. The BW_SEL pin has a 100 kΩ, on-chip pull-up resistor. Setting the BW_SEL pin open disables the low-pass filter. LOS_INV (LOSE OF SIGNAL_INVERT) MODE Some applications, such as SFF, need the LOS assertion and deassertion voltage reversed. When the LOS_INV pin is pulled to logic high, the LOS output assertion is pulled down to electrical low. The LOS_INV pin has a 100 kΩ on-chip, pull-down resistor. Rev. B | Page 10 of 16 |
Podobny numer części - ADN2892_15 |
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Podobny opis - ADN2892_15 |
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