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ISL6121HIBZA Arkusz danych(PDF) 5 Page - Intersil Corporation |
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ISL6121HIBZA Arkusz danych(HTML) 5 Page - Intersil Corporation |
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5 / 16 page  5 FN9005.4 June 10, 2005 ISL6123, 24, 25, 26, 27, 28 Descriptions and Operation The ISL612X sequencer family consists of several four channel voltage sequencing controllers in various functional and personality configurations. All are designed for use in multiple-voltage systems requiring power sequencing of various supply voltages. Individual voltage rails are gated on and off by external N-Channel MOSFETs, the gates of which are driven by an internal charge pump to VDD +5.3V (VQP) in a user programmed sequence. With the four-channel ISL6123 the ENABLE must be asserted high and all four voltages to be sequenced must be above their respective user programmed Under Voltage Lock Out (UVLO) levels before programmed output turn on sequencing can begin. Sequencing and delay determination is accomplished by the choice of external cap values on the DLY_ON and DLY_OFF pins. Once all 4 UVLO inputs and ENABLE are satisfied for 10ms, the four DLY_ON caps are simultaneously charged with 1 µA current sources to the DLY_Vth level of 1.27V. As each DLY_ON pin reaches the DLY_Vth level its associated GATE will then turn-on with a 1 µA source current to the VQP voltage of VDD+5.3V. Thus all four GATEs will sequentially turn on. Once at DLY_Vth the DLY_ON pins will discharge to be ready when next needed. After the entire turn on sequence has been completed and all GATEs have reached the charge pumped voltage (VQP), a 160ms delay is started to ensure stability after which the RESET# output will be released to go high. Subsequent to turn-on, if any input falls below its UVLO point for longer than the glitch filter period (~30 µs) this is considered a fault. RESET# and SYSRST# are pulled low and all GATEs are simultaneously also pulled low. In this mode the GATEs are pulled low with 88mA. Normal shutdown mode is entered when no UVLO is violated and the ENABLE is deasserted. When ENABLE is deasserted, RESET# is asserted and pulled low. Next, all four shutdown ramp caps on the DLY_OFF pins are charged with a 1 µA source and when any ramp-cap reaches DLY_Vth, a latch is set and a current is sunk on the respective GATE pin to turn off its external MOSFET. When the GATE voltage is approximately 0.6V, the GATE is pulled down the rest of the way at a higher current level. Each individual external FET is thus turned off removing the voltages from the load in the programmed sequence. The ISL6123 and ISL6124 have the same functionality except for the ENABLE active polarity with the ISL6124 having an ENABLE# input. Additionally the ISL6123 also has an ultra low power sleep state when ENABLE is low. The ISL6125 has the same personality as the ISL6124 but instead of charged pump driven GATE outputs it has open drain LOGIC outputs that can be pulled up to a maximum of VDD. The ISL6126 is unique in that it’s sequence on is not time determined but voltage determined. It’s personality is that each of the four channels operates independently so that once the IC is biased and any one of the UVLO inputs is greater than the 0.63V internal reference, and ENABLE# input is also satisfied the GATE for the associated UVLO input will turn-on. In turn the other UVLO inputs need to be satisfied for the associated GATEs to turn-on. 150ms after all GATEs are fully on (GATE voltage = VQP) the RESET# is released to go high. The UVLO inputs can be driven by either a previously turned on output rail offering a voltage determined sequence or by logic signal inputs. Any subsequent UVLO level < its programmed level will pull the RESET# output low (if previously released), but will not latch-off the other outputs. Predetermined turn-off is accomplished by signaling ENABLE# high, this will cause RESET# to latch low and all four GATE outputs to follow the programmed turn off sequence similar to a ISL6124. The ISL6127 is a four channel sequencer pre-programmed for A-B-C-D turn-on and D-C-B-A turn-off. After all four UVLO and ENABLE# inputs are satisfied for ~10ms, the sequencing starts and the next GATE in the sequence starts to ramp up once the GATE Current Range IGATE_range Within IC IGATE max-min - - 0.35 µA GATE Turn-On/Off Current Temp. Coeff. TC_IGATE -0.2 - nA/°C GATE Pull-Down High Current IGATEoff_h GATE = VDD, UVLO = 0V - 88 - mA GATE High Voltage VGATEh Gate High Voltage VDD+5V VDD+5.3V - V GATE Low Voltage VGATE_ Gate Low Voltage, VDD = 1V - 0 0.1 V BIAS IC Supply Current IVDD_5V VDD = 5V - 0.20 0.5 mA IC Supply Current IVDD_3.3V VDD = 3.3V - 0.14 - mA IC Supply Current IVDD_1.5V VDD = 1.5V - 0.10 - mA ISL6123 Stand By IC Supply Current IVDD_sb VDD = 5V, ENABLE = 0V - - 1 µA VDD Power On Reset VDD_POR - - 1 V Electrical Specifications VDD = 1.5V to +5V, TA = TJ = -40°C - 85°C, Unless Otherwise Specified. (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128 |
Podobny numer części - ISL6121HIBZA |
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Podobny opis - ISL6121HIBZA |
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