TPS-1

INTERNAL BLOCK DIAGRAM

R19DS0069EJ0103 Rev. 1.03

page 2 of 37

Jul 17, 2014

INTERNAL BLOCK DIAGRAM

The block diagram shows the internal structure and main components of the TPS-1.

The additional serial boot Flash component, the oscillator and the physical adaptation for the Ethernet interfaces are not

listed.

PHY 2

PHY 1

SPI

Slave

Parallel

Interface

8 / 16 Bit

Host Interface

PROFINET IO CPU

Boot-

ROM

ARM

Core

RAM

PROFINET IO Core

Time Sync

IRT Switch

Protocol Handling

LAN signals

(I2C-bus, link and

Activity), Test Sync

Clock Signals T1 to T6

Clock

Unit

25 MHz

MDI

MDI

Link1, Act1, Link2, Act2

Test Sync

JTAG / Debug

Serial Flash

(SPI Slave)

Host Interface /

Parallel - Serial

48 GPIO

Status Info

LEDs

Control Signals

Power Supply

Switching Regulator

1.0 V

3.3 V

1.5 V