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ADSP-BF522BBCZ-3A Arkusz danych(PDF) 8 Page - Analog Devices

Numer części ADSP-BF522BBCZ-3A
Szczegółowy opis  Blackfin Embedded Processor
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ADSP-BF522BBCZ-3A Arkusz danych(HTML) 8 Page - Analog Devices

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Rev. D
|
Page 8 of 88
|
July 2013
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
Event Control
The processor provides a very flexible mechanism to control the
processing of events. In the CEC, three registers are used to
coordinate and control events. Each register is 16 bits wide.
• CEC interrupt latch register (ILAT) — Indicates when
events have been latched. The appropriate bit is set when
the processor has latched the event and cleared when the
event has been accepted into the system. This register is
updated automatically by the controller, but it may be writ-
ten only when its corresponding IMASK bit is cleared.
• CEC interrupt mask register (IMASK) — Controls the
masking and unmasking of individual events. When a bit is
set in the IMASK register, that event is unmasked and is
processed by the CEC when asserted. A cleared bit in the
IMASK register masks the event, preventing the processor
from servicing the event even though the event may be
latched in the ILAT register. This register may be read or
written while in supervisor mode. (Note that general-
purpose interrupts can be globally enabled and disabled
with the STI and CLI instructions, respectively.)
• CEC interrupt pending register (IPEND) — The IPEND
register keeps track of all nested events. A set bit in the
IPEND register indicates the event is currently active or
nested at some level. This register is updated automatically
by the controller but may be read while in supervisor mode.
The SIC allows further control of event processing by providing
three pairs of 32-bit interrupt control and status registers. Each
register contains a bit corresponding to each of the peripheral
interrupt events shown in Table 3 on Page 7.
• SIC interrupt mask registers (SIC_IMASKx) — Control the
masking and unmasking of each peripheral interrupt event.
When a bit is set in these registers, that peripheral event is
OTP Memory Interrupt
IVG11
26
4
IAR3
IMASK0, ISR0, IWR0
GP Counter
IVG11
27
4
IAR3
IMASK0, ISR0, IWR0
DMA Channel 1 (MAC RX/HOSTDP)
IVG11
28
4
IAR3
IMASK0, ISR0, IWR0
Port H Interrupt A
IVG11
29
4
IAR3
IMASK0, ISR0, IWR0
DMA Channel 2 (MAC TX/NFC)
IVG11
30
4
IAR3
IMASK0, ISR0, IWR0
Port H Interrupt B
IVG11
31
4
IAR3
IMASK0, ISR0, IWR0
Timer 0
IVG12
32
5
IAR4
IMASK1, ISR1, IWR1
Timer 1
IVG12
33
5
IAR4
IMASK1, ISR1, IWR1
Timer 2
IVG12
34
5
IAR4
IMASK1, ISR1, IWR1
Timer 3
IVG12
35
5
IAR4
IMASK1, ISR1, IWR1
Timer 4
IVG12
36
5
IAR4
IMASK1, ISR1, IWR1
Timer 5
IVG12
37
5
IAR4
IMASK1, ISR1, IWR1
Timer 6
IVG12
38
5
IAR4
IMASK1, ISR1, IWR1
Timer 7
IVG12
39
5
IAR4
IMASK1, ISR1, IWR1
Port G Interrupt A
IVG12
40
5
IAR5
IMASK1, ISR1, IWR1
Port G Interrupt B
IVG12
41
5
IAR5
IMASK1, ISR1, IWR1
MDMA Stream 0
IVG13
42
6
IAR5
IMASK1, ISR1, IWR1
MDMA Stream 1
IVG13
43
6
IAR5
IMASK1, ISR1, IWR1
Software Watchdog Timer
IVG13
44
6
IAR5
IMASK1, ISR1, IWR1
Port F Interrupt A
IVG13
45
6
IAR5
IMASK1, ISR1, IWR1
Port F Interrupt B
IVG13
46
6
IAR5
IMASK1, ISR1, IWR1
SPI Status
IVG7
47
0
IAR5
IMASK1, ISR1, IWR1
NFC Status
IVG7
48
0
IAR6
IMASK1, ISR1, IWR1
HOSTDP Status
IVG7
49
0
IAR6
IMASK1, ISR1, IWR1
Host Read Done
IVG7
50
0
IAR6
IMASK1, ISR1, IWR1
Reserved
IVG10
51
3
IAR6
IMASK1, ISR1, IWR1
USB_INT0 Interrupt
IVG10
52
3
IAR6
IMASK1, ISR1, IWR1
USB_INT1 Interrupt
IVG10
53
3
IAR6
IMASK1, ISR1, IWR1
USB_INT2 Interrupt
IVG10
54
3
IAR6
IMASK1, ISR1, IWR1
USB_DMAINT Interrupt
IVG10
55
3
IAR6
IMASK1, ISR1, IWR1
Table 3. System Interrupt Controller (SIC) (Continued)
Peripheral Interrupt Event
General Purpose
Interrupt (at RESET)Peripheral Interrupt ID
Default
Core Interrupt ID SIC Registers


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