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ADSP-BF523BBCZ-5A Arkusz danych(PDF) 9 Page - Analog Devices |
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ADSP-BF523BBCZ-5A Arkusz danych(HTML) 9 Page - Analog Devices |
9 / 88 page Rev. D | Page 9 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 unmasked and is processed by the system when asserted. A cleared bit in the register masks the peripheral event, pre- venting the processor from servicing the event. • SIC interrupt status registers (SIC_ISRx) — As multiple peripherals can be mapped to a single event, these registers allow the software to determine which peripheral event source triggered the interrupt. A set bit indicates the peripheral is asserting the interrupt, and a cleared bit indi- cates the peripheral is not asserting the event. • SIC interrupt wakeup enable registers (SIC_IWRx) — By enabling the corresponding bit in these registers, a periph- eral can be configured to wake up the processor, should the core be idled or in sleep mode when the event is generated. For more information see Dynamic Power Management on Page 14. Because multiple interrupt sources can map to a single general- purpose interrupt, multiple pulse assertions can occur simulta- neously, before or during interrupt processing for an interrupt event already detected on this interrupt input. The IPEND register contents are monitored by the SIC as the interrupt acknowledgement. The appropriate ILAT register bit is set when an interrupt rising edge is detected (detection requires two core clock cycles). The bit is cleared when the respective IPEND register bit is set. The IPEND bit indicates that the event has entered into the proces- sor pipeline. At this point the CEC recognizes and queues the next rising edge event on the corresponding event input. The minimum latency from the rising edge transition of the general- purpose interrupt to the IPEND output asserted is three core clock cycles; however, the latency can be much higher, depend- ing on the activity within and the state of the processor. DMA CONTROLLERS The processor has multiple, independent DMA channels that support automated data transfers with minimal overhead for the processor core. DMA transfers can occur between the processor's internal memories and any of its DMA-capable peripherals. Additionally, DMA transfers can be accomplished between any of the DMA-capable peripherals and external devices connected to the external memory interfaces, including the SDRAM controller and the asynchronous memory control- ler. DMA-capable peripherals include the Ethernet MAC, NFC, HOSTDP, USB, SPORTs, SPI port, UARTs, and PPI. Each indi- vidual DMA-capable peripheral has at least one dedicated DMA channel. The processor DMA controller supports both one-dimensional (1-D) and two-dimensional (2-D) DMA transfers. DMA trans- fer initialization can be implemented from registers or from sets of parameters called descriptor blocks. The 2-D DMA capability supports arbitrary row and column sizes up to 64K elements by 64K elements, and arbitrary row and column step sizes up to ±32K elements. Furthermore, the column step size can be less than the row step size, allowing implementation of interleaved data streams. This feature is especially useful in video applications where data can be de- interleaved on the fly. Examples of DMA types supported by the processor DMA con- troller include: • A single, linear buffer that stops upon completion. • A circular, auto-refreshing buffer that interrupts on each full or fractionally full buffer. • 1-D or 2-D DMA using a linked list of descriptors. • 2-D DMA using an array of descriptors, specifying only the base DMA address within a common page. In addition to the dedicated peripheral DMA channels, there are two memory DMA channels provided for transfers between the various memories of the processor system. This enables trans- fers of blocks of data between any of the memories—including external SDRAM, ROM, SRAM, and flash memory—with mini- mal processor intervention. Memory DMA transfers can be controlled by a very flexible descriptor-based methodology or by a standard register-based autobuffer mechanism. The processor also has an external DMA controller capability via dual external DMA request pins when used in conjunction with the external bus interface unit (EBIU). This functionality can be used when a high speed interface is required for external FIFOs and high bandwidth communications peripherals such as USB 2.0. It allows control of the number of data transfers for memory DMA. The number of transfers per edge is program- mable. This feature can be programmed to allow memory DMA to have an increased priority on the external bus relative to the core. HOST DMA PORT The host port interface allows an external host to be a DMA master to transfer data in and out of the device. The host device masters the transactions and the Blackfin processor is the DMA slave. The host port is enabled through the PAB interface. Once enabled, the DMA is controlled by the external host, which can then program the DMA to send/receive data to any valid inter- nal or external memory location. The host port interface controller has the following features. • Allows external master to configure DMA read/write data transfers and read port status. • Uses asynchronous memory protocol for external interface. • 8-/16-bit external data interface to host device. • Half duplex operation. • Little-/big-endian data transfer. • Acknowledge mode allows flow control on host transactions. • Interrupt mode guarantees a burst of FIFO depth host transactions. REAL-TIME CLOCK The real-time clock (RTC) provides a robust set of digital watch features, including current time, stopwatch, and alarm. The RTC is clocked by a 32.768 kHz crystal external to the Blackfin processor. Connect RTC pins RTXI and RTXO with external |
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