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ADSP-BF526C Arkusz danych(PDF) 6 Page - Analog Devices |
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ADSP-BF526C Arkusz danych(HTML) 6 Page - Analog Devices |
6 / 36 page Rev. A | Page 6 of 36 | March 2010 ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C The programmer can simultaneously load the volume control of both channels by writing to the LRHPBOTH (Register R2, Bit D8) and RLHPBOTH (Register R3, Bit D8) bits of the left- or right-channel DAC volume registers. The maximum output level of the headphone outputs is 1.0 V rms when AVDD and HPVDD = 3.3 V. To suppress audi- ble pops and clicks, the headphone and line outputs are held at the VMID dc voltage level when the device is set to standby mode or when the headphone outputs are muted. The stereo line outputs of the codec, the LOUT and ROUT pins, can drive a load impedance of 10 k Ω and 50 pF. The line output signal levels are not adjustable at the output mixer, which has a fixed gain of 0 dB. The maximum output level of the line out- puts is 1.0 V rms when AVDD = 3.3 V. DIGITAL AUDIO INTERFACE The digital audio input can support the following digital audio communication protocols: right-justified mode, left-justified mode, I2S mode, and frame sync mode. See Figure 6 on Page 6 through Figure 10 on Page 7. The mode selection is performed by writing to the FORMAT bits of the digital audio interface register (Register R7, Bit D1 and Bit D0). All modes are MSB first and operate with data of 16 to 32 bits. Figure 6. Left-Justified Audio Input Mode Figure 7. Right-Justified Audio Input Mode ADCLRC/ DACLRC CODEC_BCLK ADCDAT/ DACDAT 1234 N X X X X N 12 LEFT CHANNEL 3 RIGHT CHANNEL 1/ fS X = DON’T CARE. ADCLRC/ DACLRC CODEC_BCLK ADCDAT/ DACDAT LEFT CHANNEL RIGHT CHANNEL 1/ fS X = DON’T CARE. XN X 3 2 1 XXN 4 4321 |
Podobny numer części - ADSP-BF526C_15 |
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Podobny opis - ADSP-BF526C_15 |
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