LF9502 datasheet(2/7 Pages) LODEV

Numer części	LF9502

Szczegółowy opis	2K Programmable Line Buffer

Download	7 Pages

Scroll/Zoom	100%

Producent	LODEV [LOGIC Devices Incorporated]

Strona internetowa	http://www.logicdevices.com

Logo

2 / 7 page

DEVICES INCORPORATED

LF9502

2K Programmable Line Buffer

2

08/16/2000–LDS.9502-G

Video Imaging Products

Outputs

DO9-0 — Data Output

The 10-bit data output appears on

DO9-0 on the Nth clock cycle, where N

is the overall delay (desired delay).

Controls

LCEN — Length Control Enable

When LCEN is driven LOW, the next

active clock edge will cause the

loading of the delay value present at

the LC10-0 input.

OE — Output Enable

The Output Enable controls the state

of DO9-0. Driving OE LOW enables

the output port. When OE is HIGH,

DO9-0 is placed in a high-impedance

state. The internal transfer of data is

not affected by this control.

MODSEL — Mode Select

The Mode Select pin is used to choose

the desired mode of operation: data

delay mode or data recirculation

mode. Driving MODSEL LOW places

the device in the delay mode. The

device operates as a programmable

pipeline register. New data from the

DI9-0 input is loaded on every active

edge of CLK. Driving MODSEL

HIGH places the device in the data

recirculation mode. The device

operates as a programmable circular

buffer. The output of the device is

routed back to the input. MODSEL

may be changed during device

operation (synchronously), however,

the required setup and hold times,

with respect to CLK, must be met.

SIGNAL DEFINITIONS

Power

VCC and GND

+5 V power supply. All pins must be

connected.

Clock

CLK — Master Clock

The active edge of CLK, selected by

CLKSEL, strobes all registers. All

timing specifications are referenced to

the active edge of CLK.

Inputs

DI9-0 — Data Input

10-bit data, from the data input, is

latched into the device on the active

edge of CLK when MODSEL is LOW.

LC10-0 — Length Control Input

The 11-bit value is used to specify the

length of the delay buffer, between

DI9-0 and DO9-0, or the amount of

recirculation delay. An integer value

ranging from 0 to 2047 is used to

select a delay ranging from 2 to 2049

clock cycles. The value placed on the

LC10-0 inputs is equal to the desired

delay minus 2. The data presented on

LC10-0 is loaded into the device on the

active edge of CLK, selected by

CLKSEL, in conjunction with LCEN

being driven LOW.

CLKSEL — Clock Select

The CLKSEL control allows the

selection of the active edge of CLK. A

LOW on CLKSEL selects negative-

edge triggering of the device. Driving

CLKSEL HIGH selects positive-edge

triggering. All timing specifications

are referrenced to the selected active

edge of CLK.

CLKEN — Clock Enable

The Clock Enable control enables and

disables the CLK input. Driving

CLKEN LOW enables CLK and causes

the device to operate in a normal

fashion. When CLKEN is HIGH, CLK

is disabled and the device will hold all

internal operations and data. CLKEN

may be changed during device

operation (synchronously), however,

the required setup and hold times,

with respect to CLK, must be met.

The changing of CLKEN takes effect

on the active edge of CLK following

the edge in which it was latched.

Podobny numer części - LF9502

Producent	Numer części	Arkusz danych	Szczegółowy opis
LOGIC Devices Incorpora...	LF9501	52Kb / 7P	Programmable Line Buffer
	LF9501JC20	52Kb / 7P	Programmable Line Buffer
	LF9501JC25	52Kb / 7P	Programmable Line Buffer

More results

Podobny opis - LF9502

Producent	Numer części	Arkusz danych	Szczegółowy opis
LOGIC Devices Incorpora...	LF9501	52Kb / 7P	Programmable Line Buffer
Intersil Corporation	HSP9501	372Kb / 8P	Programmable Data Buffer
Renesas Technology Corp	5P1105	743Kb / 32P	Programmable Fanout Buffer Aug 1, 2022
Renesas Technology Corp	HSP9501	657Kb / 8P	Programmable Data Buffer Aug 2004
Integrated Device Techn...	5P1105	479Kb / 32P	Programmable Fanout Buffer
Renesas Technology Corp	5P1103	1Mb / 31P	Programmable Fanout Buffer Aug 1, 2022
Intersil Corporation	HSP9501	49Kb / 8P	Programmable Data Buffer
Renesas Technology Corp	M66305AP	2Mb / 11P	TOGGLE LINE BUFFER
Cypress Semiconductor	CY7B991	515Kb / 19P	Programmable Skew Clock Buffer
Cypress Semiconductor	CY7B991	520Kb / 21P	Programmable Skew Clock Buffer

More results

LF9502 Arkusz danych(PDF) 2 Page - LOGIC Devices Incorporated

LF9502 Arkusz danych(HTML) 2 Page - LOGIC Devices Incorporated

Podobny numer części - LF9502

Podobny opis - LF9502

Html Pages

1 2 3 4 5 6 7

Arkusz danych Pobierz

Link URL