Datasheet

8/18

TSZ02201-0Q3Q0JZ00270-1-2

© 2015 ROHM Co., Ltd. All rights reserved.

22.Jun.2015 Rev.002

www.rohm.com

TSZ22111 • 15 • 001

BD14000EFV-C

Function description and items that need attention

1.

Setting the operation mode from the Enable terminal

It is possible to control the cell balancer function ON/OFF setting of the IC via the operation mode setting pin (ENIN)

The settings for each input terminal is shown on the following table

Input

Balancer Setting

Remarks

ENIN

ON/OFF

0

OFF

Standby

1

ON

Operating

When standby, only the internal power supply (VREG) is operational.

When operating, the other blocks are also operational.

2.

Detection Voltage Setting

By using the detection voltage setting terminal pins (VSET0,1 and 2), setting the cell balance start detection voltage

(VCB) and over-voltage detection voltage 1,2 (VOVLO1,2) is possible. Output for each input terminal is shown on the

following table:

Input

Output

VSET2

VSET1

VSET0

VCB[V]

VOVLO1[V]

VOVLO2[V]

0

0

0

2.4

or

or

0

0

1

2.5

0

1

0

2.6

0

1

1

2.7

1

0

0

2.8

1

0

1

2.9

1

1

0

3.0

1

1

1

3.1

(*1)

：

OVLOSEL=’L’ condition

(*2)

：

OVLOSEL=’H’ condition

3.

Over-Voltage Flag output

The Over- Voltage Detection Output Terminals (VO_OVLO1, 2) are the OR output signals of the chip’s built-in over-

voltage detection 1 and 2 output signals.

The flag output logic is shown on the following tables:

Built-In Over-

Voltage

Detection

(OVLO1)

Output

(VO_OVLO1)

Non-Detection

Hi-Z

Detection

L

Built-In Over-

Voltage

Detection

(OVLO2)

Output

(VO_OVLO2)

Non-Detection

Hi-Z

Detection

L