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74ALVC573 Arkusz danych(PDF) 1 Page - NXP Semiconductors |
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74ALVC573 Arkusz danych(HTML) 1 Page - NXP Semiconductors |
1 / 17 page 1. General description The 74ALVC573 is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-state true outputs for bus-oriented applications. A latch enable (LE) input and an outputs enable (OE) input are common to all latches. When pin LE is HIGH, data at the D-inputs (pins D0 to D7) enters the latches. In this condition, the latches are transparent, that is, a latch output will change each time its corresponding D-input changes. When pin LE is LOW, the latches store the information that was present at the D-inputs one set-up time preceding the HIGH-to-LOW transition of pin LE. When pin OE is LOW, the contents of the eight latches are available at the Q-outputs (pins Q0 to Q7). When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of input pin OE does not affect the state of the latches. The 74ALVC573 is functionally identical to the 74ALVC373, but has a different pin arrangement. 2. Features s Wide supply voltage range from 1.65 V to 3.6 V s 3.6 V tolerant inputs/outputs s CMOS low power consumption s Direct interface with TTL levels (2.7 V to 3.6 V) s Power-down mode s Latch-up performance exceeds 250 mA s Complies with JEDEC standards: x JESD8-7 (1.65 V to 1.95 V) x JESD8-5 (2.3 V to 2.7 V) x JESD8B/JESD36 (2.7 V to 3.6 V) s ESD protection: x HBM JESD22-A114E exceeds 2000 V x MM JESD22-A 115-A exceeds 200 V 74ALVC573 Octal D-type transparent latch; 3-state Rev. 03 — 26 October 2007 Product data sheet |
Podobny numer części - 74ALVC573_15 |
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Podobny opis - 74ALVC573_15 |
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