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74AUP1G125 Arkusz danych(PDF) 2 Page - NXP Semiconductors |
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74AUP1G125 Arkusz danych(HTML) 2 Page - NXP Semiconductors |
2 / 25 page 74AUP1G125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 6 — 15 August 2012 2 of 25 NXP Semiconductors 74AUP1G125 Low-power buffer/line driver; 3-state 3. Ordering information 4. Marking [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP1G125GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1 74AUP1G125GM 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1 1.45 0.5 mm SOT886 74AUP1G125GF 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1 1 0.5 mm SOT891 74AUP1G125GN 40 C to +125 C XSON6 extremely thin small outline package; no leads; 6 terminals; body 0.9 1.0 0.35 mm SOT1115 74AUP1G125GS 40 C to +125 C XSON6 extremely thin small outline package; no leads; 6 terminals; body 1.0 1.0 0.35 mm SOT1202 74AUP1G125GX 40 C to +125 C X2SON5 X2SON5: plastic thermal enhanced extremely thin small outline package; no leads; 5 terminals; body 0.8 0.8 0.35 mm SOT1226 Table 2. Marking Type number Marking code[1] 74AUP1G125GW pM 74AUP1G125GM pM 74AUP1G125GF pM 74AUP1G125GN pM 74AUP1G125GS pM 74AUP1G125GX pM Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram mna118 AY 2 1 4 OE mna119 1 4 2 EN 001aad068 A OE Y |
Podobny numer części - 74AUP1G125_15 |
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Podobny opis - 74AUP1G125_15 |
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