SM3-8RG5 Data Sheet #:

TM088

Page 7 of 32

Rev:

07 Date: 09/06/11

© Copyright 2011 The Connor-Winfield Corp. All Rights Reserved

Specifications subject to change without notice

Detailed Description continued

TheM/SOutputortheOutput1ofeachdevicemaybecross-connectedtotheotherdevice’sM/SRefinput.Thedeviceauto-

detectsthefrequencyontheM/SRefinput.MasterorslavestateofadeviceisdeterminedbytheM/Spin.Thus,master/slavestateis

alwaysmanuallycontrolledbytheapplication.Themastersynchronizestotheselectedinputreference,whiletheslavesynchronizes

totheM/SRefinput.(Notethat8kHzframephasealignmentismaintainedacrossamaster/slavepairofdevicesonlyifM/SOutputis

usedasthecrosscouplesignal.)

Theunitoperatinginslavemodelocksonandphase-alignstothecross-referenceclock(M/SOutputorOutput1)fromtheunit

inmastermode.Thephaseskewbetweentheinputcross-referenceandtheoutputclockfortheslaveunitistypicallylessthan±1ns

(under±3nsindynamicsituations,includingreferencejitterandwander).

PerfectphasealignmentofthetwoOutput1outputclockswouldrequirenodelayonthecross-referenceclockconnection.

Toaccommodatepathlengthdelays,theSM3-8RG5providesaprogrammablephaseskewfeature.Theslave’sOutput1orM/S

Outputmaybephaseshifted-32nSto+31.75nSrelativetoM/SInputaccordingtothecontentsoftheMS_Phase_Offsetregisterto

compensateforthepathlengthoftheM/SOutputorOutput1toM/SInputconnection.Thisoffsetmaythereforebeprogrammedto

exactlycompensatefortheactualpathlengthdelayassociatedwiththeparticularapplication’scross-referencetraces.Theoffsetmay

furtherbeadjustedtoaccommodateanyoutputclockdistributionpathdelaydifferences.Thus,master/slaveswitcheswiththeSM3

devicesmaybeaccomplishedwithnear-zerophasehits.

Thefirsttimeaunitbecomesaslave,suchasimmediatelyafterpower-up,itsoutputclockphasestartsoutarbitrary,andwill

quicklyphase-aligntothecross-referencefromthemasterunit.Thephaseskewwillbeeliminated(orconvergedtotheprogrammed

phaseoffset)stepbystep.Thewholepull-in-and-lockprocesswillcompleteinabout60seconds.Thereisnofrequencyslew

protectioninslavemode.Inslavemode,theunit’smissionistolocktoandfollowthemaster.

Onceapairofunitshasbeenoperatinginalignedmaster/slavemode,andamaster/slaveswitchoccurs,theunitthatbecomes

masterwillmaintainitsoutputclockphaseandfrequencywhileaphasebuild-out(tothecurrentoutputclockphase)isperformedon

itsselectedreferenceinput.Therefore,asmastermodeoperationcommences,therewillbenophaseorfrequencyhitsontheclock

output.

Likewise,theunitthatbecomestheslavewillmaintainitsoutputclockfrequencyandphasefor1msecbeforestartingtofollowthe

cross-reference,protectingthedownstreamclockusersduringtheswitch.Assumingthephaseoffsetisprogrammedfortheactual

propagationdelayofthiscross-referencepath,therewillagainbenophasehitsontheoutputclockoftheunitthathastransitioned

frommastertoslave.

Master / Slave Configuration

Figure 3

STC3500

M/S_OUT / OUTPUT1

M/S_OUT / OUTPUT1

M/S REF

REFS1-8

REFS1-8

M/S REF

SM3-8RG5

2

SM3-8RG5

1

Furthermore,underregisteraccesscontrol,abackupholdoverhistoryregisterisprovided.Itmaybeloadedfromtheactive

holdoverhistoryorrestoredtotheactiveholdoverhistory.Theactiveholdoverhistorymayalsobeflushed.

Holdovermodemaybeenteredatanytime.Ifthereisnoholdoverhistoryavailable,theprioroutputfrequencywillbemaintained.

Wheninholdover,theapplicationmayread(viaregisteraccess)thetimesinceholdoverwasenterred.

Master/Slave Operation

PairsofSM3-8RG5devicesmaybeoperatedinamaster/slaveconfigurationforredundanttimingsourceapplications.Atypical

configurationisshownbelow.: