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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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STC3800 Arkusz danych(PDF) 8 Page - Connor-Winfield Corporation |
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STC3800 Arkusz danych(HTML) 8 Page - Connor-Winfield Corporation |
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8 / 48 page  Preliminary Data Sheet #: TM061 Page 8 of 48 Rev: P06 Date: 11/22/04 © Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice The STC3800 is a single chip synchronization and timing solution for the Stratum 3 and 3E Synchronous Equipment Timing Source (SETS) function in network elements. Its highly integrated design includes hardware and firmware to implement all of the necessary reference selection, monitoring, digital filtering, synthesis, and control functions. An external OCXO/TCXO, DAC, and VCXO (and optional EEPROM) complete a system level solution (see Functional Block Diagram). Up to 8 external references, each from 8 kHz to 77.76 MHz, may be equipped and monitored for signal presence and frequency offset. Additionally, a cross-couple reference input, accepting from 8 kHz to 77.76 MHz, is provided for master/slave operation. Reference selection may be manual or automatic, according to programmed priorities. All reference switches are performed in a hitless manner, and frequency ramp controls ensure smooth output signal transitions. When references are switched, the device provides a controllable phase build-out to minimize phase transitions in the output clocks. Three phase aligned output signals are provided, the first up to 155.52 MHz (determined by VCXO selection), the second fixed at 8 kHz for use as a frame signal. Both of these may also be used as a cross-couple reference for master/slave operation. In slave mode, the output phase may be adjusted from -32 to +31.75nS relative to the master, to accommodate downstream system needs, such as different clock distribution path lengths. The third phase aligned output is a 2 kHz multi-frame sync output. The fourth output is a BITS clock, selectable as either 1.544 MHz or 2.048 MHz Device operation may be in Free Run, synchronized, or Hold Over modes. In Free Run, the clock outputs are simply determined by the accuracy of the digital calibrated OCXO/TCXO. In synchronized mode, the chip phase locks to the selected input reference. While synchronized, a frequency history is accumulated. In Hold Over mode, the chip outputs are synthesized according to this history. The Digital Phase Locked Loop which provides the critical filtering and frequency/phase control functions is implemented with Connor-Winfield’s NOVA Kernel - a set of well-proven algorithms and control that meet or exceed all requirements and lead the industry in critical jitter and accuracy performance parameters. Filter bandwidth may be configured for Stratum 3 or 3E. Control functions are provided either via direct hardware signals or standard SPI or 8-bit parallel bus register interfaces. Direct hardware control provides a very simple system interface, while bus/register access provides greater visibility into a variety of registered information as well as providing more extensive programmable control capability. Detailed Description |
Podobny numer części - STC3800_15 |
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Podobny opis - STC3800_15 |
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