3.3V, 16-Bit, 200Msps High Dynamic

Performance DAC with CMOS Inputs

_______________________________________________________________________________________

3

ELECTRICAL CHARACTERISTICS (continued)

≥+25°C guaranteed by production test, <+25°C guaranteed by design

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

77

73

72

≥+25°C

68

76

71

Spurious-Free Dynamic Range to

Nyquist

SFDR

71

dBc

-88

Two-Tone IMD

TTIMD

-74

dBc

Four-Tone IMD, 1MHz Frequency

Spacing, GSM Model

FTIMD

-12dB FS

-82

dBc

Adjacent Channel Leakage

Power Ratio, 4.1MHz Bandwidth,

WCDMA Model

ACLR

184.32MHz

74

dB

Output Bandwidth

(Note 2)

450

MHz

REFERENCE

Internal Reference Voltage Range

1.1

1.21

1.34

V

Reference Input Compliance

Range

0.125

1.25

V

Reference Input Resistance

10

k

Ω

Reference Voltage Drift

±50

ppm/

°C

ANALOG OUTPUT TIMING

Output Fall Time

90% to 10% (Note 3)

375

ps

Output Rise Time

10% to 90% (Note 3)

375

ps

Output Voltage Settling Time

Output settles to 0.025% FS (Note 3)

11

ns

Output Propagation Delay

(Note 3)

1.8

ns

Glitch Energy

1

pV-s

30

Output Noise

30

pA/

√Hz

TIMING CHARACTERISTICS

Data to Clock Setup Time

Referenced to rising edge of clock (Note 4)

0.4

ns

Data to Clock Hold Time

Referenced to rising edge of clock (Note 4)

1.25

ns