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ADS58J89IRGCR Arkusz danych(PDF) 11 Page - Texas Instruments

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Numer części ADS58J89IRGCR
Szczegółowy opis  ADS58J89 Quad Channel 14-Bit 250/500 MSPS Receiver and Feedback IC
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Producent  TI [Texas Instruments]
Strona internetowa  http://www.ti.com
Logo TI - Texas Instruments

ADS58J89IRGCR Arkusz danych(HTML) 11 Page - Texas Instruments

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Power Supplies
SRESETb
SDENb
t1
t2
t3
ADS58J89
www.ti.com
SBAS659 – NOVEMBER 2014
6.10 Timing Requirements
MIN
TYP
MAX
UNIT
DIGITAL INPUTS:
SRESETb, SCLK, SDENb, SDATA, ENABLE, OVRA, OVRC, SYSREFCDP, SYSREFCDM
High-level input voltage
1.2
V
All digital inputs support 1.8-V and 3.3-V logic
levels
Low-level input voltage
0.4
V
High-level input current
50
µA
Low-level input current
–50
µA
Input capacitance
4
pF
DIGITAL OUTPUTS:
SDOUT, OVRA, OVRB, OVRC, OVRD
High-level output voltage
ILoad = –100 µA
DVDD – 0.2
DVDD
V
Low-level output voltage
0.2
V
DIGITAL INPUTS:
SYNCbABP/M, SYNCbCDP/M, SYSREFABP/M, SYSREFCDP/M
Input voltage VID
250
350
450
mV
Input common mode voltage VCM
0.4
0.9
1.4
V
tS_SYSREFxx
Referenced to rising edge of input clock
100
ps
tH_SYSREFxx
Referenced to rising edge of input clock
100
ps
6.11 Reset Timing
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t1
Power-on delay
Delay from power up to active-low RESET pulse
3
ms
t2
Reset pulse duration
Active-low RESET pulse duration
20
ns
t3
Register write delay
Delay from RESET disable to SDENb active
100
ns
Figure 1. Reset Timing Diagram
Copyright © 2014, Texas Instruments Incorporated
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