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ML1000605D

(100V Input, Dual Output)

Radiation Performance

TID

The TID radiation performance is guaranteed by worst case analysis with radiation degradation data for

each radiation sensitive component used in the DC-DC converter. For TID radiation verification testing

(RVT) for each wafer lot for all sensitive components is part of the EEE parts requirements per table below.

Component Type

RVT Plan (applicable to all flight lots)

JANS2N2222A

LDRS 0.01 to 0.1 rad up to 200 krad per IR RVT plan

JANS2N2907A

LDRS 0.01 to 0.1 rad up to 200 krad per IR RVT plan

JANSR2N7492T2

RVT by Manufacturer (HDR)

IRHF57214SESCS

RVT by Manufacturer (HDR)

IRHLUB770Z4SCS

RVT by Manufacturer (HDR)

IRHLUB7970Z4SCS

RVT by Manufacturer (HDR)

LM124AWR

RVT by Manufacturer (ELDRS)

IS2-1009RH

RVT by Manufacturer (HDR)

LDRS 0.01 to 0.1 rad up to 100 krad per IR RVT plan

UC1845A

LDRS 0.01 to 0.1 rad/s up to 100kRad per IR RVT plan

TID RVT Plan Table

SEE

The SEE radiation performance is guaranteed by a combination of derating and mitigation at circuit level.

For mitigation at circuit level both theoretical analysis and testing with imposed SEE effects are performed.

The applicable SEE and mitigation concept is presented in table below.

The maximum output perturbation is 5% of the nominal output voltage during any SEE.

Component Type

Applicable SEE

Mitigation Concept

RH MOSFET

SEGR

Vds derating in combination with SEE SOA

curves from manufacturer data sheet

Op-Amp

SET, 15us perturbation to rail

Mitigation at circuit level (filtering)

Voltage reference

SET, 10us perturbation to rail

Mitigation at circuit level (filtering)

SET, 15us perturbation to rail

Mitigation at circuit level (filtering)

Double Pulses

Mitigation at circuit level (filtering, no

saturation of magnetic parts)

PWM

Missing Pulses

Mitigation at circuit level (filtering, no

saturation of magnetic parts)

Applicable SEE and Mitigation Methods Table