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ISL22313TFU10Z Arkusz danych(PDF) 6 Page - Intersil Corporation |
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ISL22313TFU10Z Arkusz danych(HTML) 6 Page - Intersil Corporation |
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6 / 15 page  6 FN6421.0 July 17, 2007 SERIAL INTERFACE SPECS VIL A1, A0, SDA, and SCL input buffer LOW voltage -0.3 0.3*VCC V VIH A1, A0, SDA, and SCL input buffer HIGH voltage 0.7*VCC VCC +0. 3 V Hysteresis (Note 16) SDA and SCL input buffer hysteresis 0.05*VCC V VOL (Note 16) SDA output buffer LOW voltage, sinking 4mA 00.4 V Cpin (Note 16) A1, A0, SDA, and SCL pin capacitance 10 pF fSCL SCL frequency 400 kHz tsp Pulse width suppression time at SDA and SCL inputs Any pulse narrower than the max spec is suppressed 50 ns tAA (Note 16) SCL falling edge to SDA output data valid SCL falling edge crossing 30% of VCC, until SDA exits the 30% to 70% of VCC window 900 ns tBUF (Note 16) Time the bus must be free before the start of a new transmission SDA crossing 70% of VCC during a STOP condition, to SDA crossing 70% of VCC during the following START condition 1300 ns tLOW Clock LOW time Measured at the 30% of VCC crossing 1300 ns tHIGH Clock HIGH time Measured at the 70% of VCC crossing 600 ns tSU:STA START condition setup time SCL rising edge to SDA falling edge; both crossing 70% of VCC 600 ns tHD:STA START condition hold time From SDA falling edge crossing 30% of VCC to SCL falling edge crossing 70% of VCC 600 ns tSU:DAT Input data setup time From SDA exiting the 30% to 70% of VCC window, to SCL rising edge crossing 30% of VCC 100 ns tHD:DAT Input data hold time From SCL rising edge crossing 70% of VCC to SDA entering the 30% to 70% of VCC window 0ns tSU:STO STOP condition setup time From SCL rising edge crossing 70% of VCC, to SDA rising edge crossing 30% of VCC 600 ns tHD:STO STOP condition hold time for read, or volatile only write From SDA rising edge to SCL falling edge; both crossing 70% of VCC 1300 ns tDH (Note 16) Output data hold time From SCL falling edge crossing 30% of VCC, until SDA enters the 30% to 70% of VCC window 0ns tR (Note 16) SDA and SCL rise time From 30% to 70% of VCC 20 + 0.1 * Cb 250 ns tF (Note 16) SDA and SCL fall time From 70% to 30% of VCC 20 + 0.1 * Cb 250 ns Cb (Note 16) Capacitive loading of SDA or SCL Total on-chip and off-chip 10 400 pF Rpu (Note 16) SDA and SCL bus pull-up resistor off-chip Maximum is determined by tR and tF For Cb = 400pF, max is about 2k Ω~2.5kΩ For Cb = 40pF, max is about 15k Ω~20kΩ 1k Ω Operating Specifications Over the recommended operating conditions unless otherwise specified. Limits are established by characterization. (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN (Note 18) TYP (Note 4) MAX (Note 18) UNIT ISL22313 |
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