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TDA21231 Arkusz danych(PDF) 4 Page - Infineon Technologies AG |
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TDA21231 Arkusz danych(HTML) 4 Page - Infineon Technologies AG |
4 / 19 page TDA21231 Data Sheet 3 Table 2 I/O Signals Pin No. Name Pin Type Buffer Type Function 1 PWM I +3.3 V logic PWM drive logic input The tri-state PWM input is compatible with 3.3 V. 5 BOOT I Analog Bootstrap voltage pin Connect to BOOT capacitor 6 GH O Analog High-Side Gate Test point for High Side MOSFET gate signal 7 PHASE I Analog Switch node (reference for Boot voltage) internally connected to SW pin, connect to BOOT capacitor 16 – 23 SW O Analog Switch node output High current output switching node 27 GL O Analog Low-Side Gate Test point for Low Side MOSFET gate signal 30 PHFLT# O +3.3 V logic Thermal Warning Connect through a resistor to 3.3V. When the thermal protection threshold is tripped, the PHFLT# pin is being pulled low. Leave open if not used. 31 EN I +3.3 V logic Enable signal (active high) Connect to GND to disable the IC. Table 3 Power Supply Pin No. Name Pin Type Function 8 to 11, Vin pad VIN POWER Input voltage Supply of the drain of the high-side MOSFET 29 PVCC POWER FET gate supply voltage High- and low-side gate drive supply 3 VCC POWER Logic supply voltage Bias voltage for the internal logic Table 4 Ground Pins Pin No. Name Pin Type Function 4 AGND GND Control signal ground Should be connected to PGND externally 12 – 15, 28, PGND pads PGND GND Power ground All these pins must be connected to the power GND plane through multiple low inductance vias. Table 5 Not Connected Pin No. Name Pin Type Function 2 NC – No internal connection Leave pin floating or tie to noise- free voltage of 0 (GND) … 7 V. 24, 25, 26 NC – No internal connection Options: Leave floating, tie to GND or SW |
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