C1 =

'V

0.15A x 3.57 Ps

2.0V

=

= 0.268 PF

SM72485

www.ti.com

SNVS697D – JANUARY 2011 – REVISED APRIL 2013

ESR and R3: A low ESR for C2 is generally desirable so as to minimize power losses and heating within the

capacitor. However, the regulator requires a minimum amount of ripple voltage at the feedback input for proper

loop operation. For the SM72485 the minimum ripple required at pin 5 is 25 mV p-p, requiring a minimum ripple

less than this, R3 is inserted as shown in the Block Diagram. R3’s value, along with C2’s ESR, must result in at

least 25 mV p-p ripple at pin 5. Generally, R3 will be 0.5 to 4.0

Ω.

normal off-time, which occurs at maximum input voltage. Using Equation 4, the minimum on-time is 476 ns,

yielding an off-time of 3.8 µs (at 234 kHz). Due to the 25% tolerance on the on-time, the off-time tolerance is also

25%, yielding a maximum off-time of 4.75 µs. Allowing for the response time of the current limit detection circuit

(350 ns) increases the maximum off-time to 5.1 µs. This is increased an additional 25% to 6.4 µs to allow for the

resistor will be used.

D1: The important parameters are reverse recovery time and forward voltage. The reverse recovery time

determines how long the reverse current surge lasts each time the buck switch is turned on. The forward voltage

drop is significant in the event the output is short-circuited as it is only this diode’s voltage which forces the

inductor current to reduce during the forced off-time. For this reason, a higher voltage is better, although that

affects efficiency. A good choice is a Schottky power diode, such as the DFLS1100. D1’s reverse voltage rating

must be at least as great as the maximum Vin, and its current rating be greater than the maximum current limit

threshold (360 mA).

C1: This capacitor’s purpose is to supply most of the switch current during the on-time, and limit the voltage

ripple at Vin, on the assumption that the voltage source feeding Vin has an output impedance greater than zero.

At maximum load current, when the buck switch turns on, the current into pin 8 will suddenly increase to the

lower peak of the output current waveform, ramp up to the peak value, then drop to zero at turn-off. The average

input current during this on-time is the load current (150 mA). For a worst case calculation, C1 must supply this

average load current during the maximum on-time. To keep the input voltage ripple to less than 2V (for this

exercise), C1 calculates to:

(8)

Quality ceramic capacitors in this value have a low ESR which adds only a few millivolts to the ripple. It is the

capacitance which is dominant in this case. To allow for the capacitor’s tolerance, temperature effects, and

voltage effects, a 1.0 µF, 100V, X7R capacitor will be used.

C4: The recommended value is 0.01µF for C4, as this is appropriate in the majority of applications. A high quality

ceramic capacitor, with low ESR is recommended as C4 supplies the surge current to charge the buck switch

gate at turn-on. A low ESR also ensures a quick recharge during each off-time. At minimum Vin, when the on-

time is at maximum, it is possible during start-up that C4 will not fully recharge during each 300 ns off-time. The

circuit will not be able to complete the start-up, and achieve output regulation. This can occur when the

sufficient voltage across the buck switch driver during each on-time.

ESR, 0.1µF ceramic chip capacitor is recommended, located close to the SM72485.

FINAL CIRCUIT

The final circuit is shown in Figure 12. The circuit was tested, and the resulting performance is shown in

Figure 13 and Figure 14.

PC BOARD LAYOUT

The SM72485 regulation and over-voltage comparators are very fast, and as such will respond to short duration

noise pulses. Layout considerations are therefore critical for optimum performance. The components at pins 1, 2,

3, 5, and 6 should be as physically close as possible to the IC, thereby minimizing noise pickup in the PC tracks.

The current loop formed by D1, L1, and C2 should be as small as possible. The ground connection from D1 to

C1 should be as short and direct as possible.

Copyright © 2011–2013, Texas Instruments Incorporated

Submit Documentation Feedback

11

Product Folder Links: SM72485