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UC2825A-EP Arkusz danych(PDF) 2 Page - Texas Instruments |
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UC2825A-EP Arkusz danych(HTML) 2 Page - Texas Instruments |
2 / 21 page 4 5 6 7 3 2 1 OSC CLK/LEB RT CT RAMP EAOUT NI INV 8 9 15 SS ILIM VCC 1.25 V 10 GND (60%) 1.0 V E/A 1.2 V 0.2 V OVER CURRENT CURRENT LIMIT R SD 5 V SOFT-ST ART COMPLETE R SD FAULT LATCH RESTART DELAY T 13 11 14 VC 12 PWM LATCH 9 A 250 A R S RESTART DELAY LATCH VREF 5.1 V ON/OFF UVLO 4 V INTERNAL BIAS 16 OUTA OUTB PGND 5.1 VREF 9.2V/8.4V PWM COMPARATOR UDG-02091 VREF GOOD UC2825A-EP SGLS305D – JULY 2005 – REVISED SEPTEMBER 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION TA PACKAGE(1) ORDERABLE PART NUMBER TOP-SIDE MARKING –40°C to 125°C SOIC – DW UC2825AQDWREP UC2825AQEP –55°C to 125°C SOIC – DW UC2825AMDWREP UC2825AMEP (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. BLOCK DIAGRAM 2 Submit Documentation Feedback Copyright © 2005–2010, Texas Instruments Incorporated Product Folder Link(s): UC2825A-EP |
Podobny numer części - UC2825A-EP_15 |
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Podobny opis - UC2825A-EP_15 |
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