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LC87F17C8AUWA-2H Arkusz danych(PDF) 3 Page - ON Semiconductor

Numer części LC87F17C8AUWA-2H
Szczegółowy opis  LC87F17C8A
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Producent  ONSEMI [ON Semiconductor]
Strona internetowa  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

LC87F17C8AUWA-2H Arkusz danych(HTML) 3 Page - ON Semiconductor

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 SMIIC1 : Single-master I2C/8-bit synchronous SIO
Mode 0 : Communication in single-master mode.
Mode 1 : 8-bit synchronous serial I/O (data MSB first)
Full Duplex UART
 SCUART2
<1> Data length : 7/8 bits selectable
<2> Stop bits
: 1/2 bits selectable
<3> Parity bits
: None/even parity/odd parity selectable
<4> Baudrate
: 8/3 to 8192/3 tCYC
<5> LSB first/MSB first mode selectable
<6> Capable of Smart card interface
<7> 8-level receive FIFO buffer
16-bit Cyclic Redundancy Check (CRC) Calculator
<1> User-programmable CRC polynomial equation
<2> 1 to 256 bytes can be specified
<3> LSB first/MSB first selectable
AD Converter: 12 bits × 12 channels
PWM: Variable frequency 12-bit PWM × 2 channels
Infrared Remote Control Receiver Circuit
<1> Noise rejection function (noise filter time constant: Approx. 120
s when the 32.768 kHz crystal oscillator
is selected as the reference clock)
<2> Supports data encoding systems such as PPM (Pulse Position Modulation) and Manchester encoding.
<3> X'tal HOLD mode release function
USB Interface
 Host Controller × 2 ports
<1> Supports Full-Speed (12 Mbps) and Low-Speed (1.5 Mbps) operation.
<2> Supports four transfer types (control transfer, bulk transfer, interrupt transfer, and isochronous transfer).
 Device Controller
<1> Supports Full-Speed operation.
<2> Supports up to 9 endpoints
Endpoint
EP0
EP1
EP2
EP3
EP4
EP5
EP6
EP7
EP8
Transfer
Type
Control
-
-
-
-
-
-
-
-
Bulk
-
Interrupt
-
Isochronous
-
Max. payload
64
64
64
64
64
64
64
1023
1023
Audio Interface
<1> Sampling frequencies (fs) : 8 kHz/11.025 kHz/12 kHz/16 kHz/22.05 kHz/24 kHz/32 kHz/44.1 kHz/48 kHz/96kHz
<2> Master clock
: 256 fs/384 fs
<3> Bit clock
: 48 fs/64 fs
<4> Data bit length : 16 bits/18 bits/20 bits/24 bits
<5> LSB first/MSB first selectable.
<6> Left justified/right justified/I2S format selectable
Watchdog Timer
 Internal counter watchdog timer
<1> Capable of generating an internal reset on an overflow of the timer running on the low-speed RC
oscillator clock, or subclock.
<2> Operation in HALT/HOLD mode can be selected from among “continue count operation,” “suspend
operation,” and “retain the count value.”


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