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SN74LS393DR2 Arkusz danych(PDF) 2 Page - ON Semiconductor |
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SN74LS393DR2 Arkusz danych(HTML) 2 Page - ON Semiconductor |
2 / 8 page SN74LS393 http://onsemi.com 2 CONNECTION DIAGRAM DIP (TOP VIEW) Clock (Active LOW Going Edge) Input to +16 (LS393) Clock (Active LOW Going Edge) Input to ÷2 (LS390) Clock (Active LOW Going Edge) Input to ÷ 5 (LS390) Master Reset (Active HIGH) Input Flip−Flop Outputs CP CP0 CP1 MR Q0 − Q3 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 1.0 U.L. 1.0 U.L. 1.5 U.L. 0.25 U.L. 5 U.L. NOTES: a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW. HIGH LOW (Note a) LOADING PIN NAMES NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 14 13 12 11 10 9 12 3456 8 7 VCC CP MR Q0 Q1 Q2 Q3 CP MR Q0 Q1 Q2 Q3 GND |
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