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TMP175AQDRQ1 Arkusz danych(PDF) 10 Page - Texas Instruments |
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TMP175AQDRQ1 Arkusz danych(HTML) 10 Page - Texas Instruments |
10 / 31 page TMP175-Q1, TMP75-Q1 SBOS759 – NOVEMBER 2015 www.ti.com 7.3.2.2 Serial Bus Address To communicate with the TMP175-Q1 and TMP75-Q1, the master must first address slave devices through a slave address byte. The slave address byte consists of seven address bits and a direction bit indicating the intent of executing a read or write operation. The TMP175-Q1 features three address pins to allow up to 27 devices to be addressed on a single bus interface. Table 2 describes the pin logic levels used to properly connect up to 27 devices. A 1 indicates that the pin is connected to the supply (VCC) and a 0 indicates that the pin is connected to GND; float indicates that the pin is left unconnected. The state of the A0, A1, and A2 pins is sampled on every bus communication and must be set prior to any activity on the interface. Table 2. Address Pins and Slave Addresses for the TMP175-Q1 A2 A1 A0 SLAVE ADDRESS 0 0 0 1001000 0 0 1 1001001 0 1 0 1001010 0 1 1 1001011 1 0 0 1001100 1 0 1 1001101 1 1 0 1001110 1 1 1 1001111 Float 0 0 1110000 Float 0 Float 1110001 Float 0 1 1110010 Float 1 0 1110011 Float 1 Float 1110100 Float 1 1 1110101 Float Float 0 1110110 Float Float 1 1110111 0 Float 0 0101000 0 Float 1 0101001 1 Float 0 0101010 1 Float 1 0101011 0 0 Float 0101100 0 1 Float 0101101 1 0 Float 0101110 1 1 Float 0101111 0 Float Float 0110101 1 Float Float 0110110 Float Float Float 0110111 10 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TMP175-Q1 TMP75-Q1 |
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