1

RFBA

16

CLK

2

VREFA

15

LDAC

3

IOUTA

14

MSB

4

AGNDA

13

VDD

5

AGNDB

12

DGND

6

IOUTB

11

CS

7

VREFB

10

RS

8

RFBB

9

SDI

DAC8812

www.ti.com

SBAS349C – AUGUST 2005 – REVISED NOVEMBER 2015

5 Device Comparison Table

DEVICE

MAXIMUM RELATIVE ACCURACY (LSB)

DAC8812C

±1

DAC8812B

±2

6 Pin Configuration and Functions

PW Package

16-Pin TSSOP

Top View

Pin Functions

PIN

I/O

DESCRIPTION

NO.

NAME

1

I

Establish voltage output for DAC A by connecting to external amplifier output.

2

I

3

O

DAC A current output

4

—

DAC A analog ground

5

—

DAC B analog ground

6

O

DAC B current output

7

I

8

I

Establish voltage output for DAC B by connecting to external amplifier output.

9

SDI

I

Serial data input; data loads directly into the shift register.

Reset pin; active-low input. Input registers and DAC registers are set to all 0s or midscale. Register data =

10

RS

I

0x0000 when MSB = 0. Register data = 0x8000 when MSB = 1 for DAC8812.

Chip-select; active-low input. Disables shift register loading when high. Transfers serial register data to input

11

CS

I

register when CS goes high. Does not affect LDAC operation.

12

DGND

—

Digital ground

MSB bit sets output to either 0 or midscale during a RESET pulse (RS) or at system power-on. Output

14

MSB

I

equals zero scale when MSB = 0 and midscale when MSB = 1. MSB pin can be permanently tied to ground

13

I

Positive power-supply input. Specified range of operation 2.7 V to 5.5 V.

Load DAC register strobe; level-sensitive active-low. Transfers all input register data to the DAC registers.

15

LDAC

I

Asynchronous active-low input. See Table 2 for operation.

16

CLK

I

Clock input. Positive edge clocks data into shift register.

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