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TPA6120A2RGYR Arkusz danych(PDF) 4 Page - Texas Instruments

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Numer części TPA6120A2RGYR
Szczegółowy opis  High Fidelity Headphone Amplifier
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Producent  TI1 [Texas Instruments]
Strona internetowa  http://www.ti.com
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TPA6120A2RGYR Arkusz danych(HTML) 4 Page - Texas Instruments

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TPA6120A2
SLOS431B – MARCH 2004 – REVISED FEBRUARY 2015
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
Supply voltage, xVCC+ to xVCC- Where x=L or R channel
9
33
V
Input voltage, VI
(2)
± VCC
Differential input voltage, VID
6
V
Minimum load impedance
8
Ω
Continuous total power dissipation
See Thermal Information
Operating free–air temperature range, TA
–40
85
°C
Operating junction temperature range, TJ
(3)
–40
150
°C
Storage Temperature, Tstg
–40
125
°C
(1)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2)
When the TPA6120A2 is powered down, the input source voltage must be kept below 600mV peak.
(3)
The TPA6120A2 incorporates an exposed PowerPAD on the underside of the chip. This acts as a heatsink and must be connected to a
thermally dissipating plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature that
could permanently damage the device. See TI Technical Brief SLMA002 for more information about utilizing the PowerPAD thermally
enhanced package.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS- For Pins: LVCC+, RVCC+,
±500
001(1)
LVCC-, RVCC
Electrostatic
For all pins except:
±2000
V(ESD)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-
V
Discharge
LVCC+, RVCC+, LVCC-,
001, all other pins
RVCC
Charged device model (CDM), per JEDEC specification JESD22-C101
±1500
(1)
Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500V HBM allows
safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
Split Supply
±5
±15
Supply voltage, VCC+ and VCC-
V
Single Supply
10
30
Load impedance
VCC = ±5V or ±15V
16
Operating free–air temperature, TA
–40
85
°C
7.4 Thermal Information
TPA6120A2
TPA6120A2
THERMAL METRIC(1)
DWP [HSOP]
RGY [VQFN]
UNIT
20 PINS
14 PINS
RθJA
Junction-to-ambient thermal resistance
44.5
49.4
RθJCtop
Junction-to-case (top) thermal resistance
55.2
62.0
RθJB
Junction-to-board thermal resistance
36.1
25.4
°C/W
ψJT
Junction-to-top characterization parameter
23.1
1.6
ψJB
Junction-to-board characterization parameter
36.2
25.5
RθJCbot
Junction-to-case (bottom) thermal resistance
7.6
6.2
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4
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Product Folder Links: TPA6120A2


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