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AD5676RACPZ-REEL7 Arkusz danych(PDF) 8 Page - Analog Devices

Numer części AD5676RACPZ-REEL7
Szczegółowy opis  Octal, 12-/16-Bit nanoDAC with ppm/째C Reference, SPI Interface
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
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AD5676RACPZ-REEL7 Arkusz danych(HTML) 8 Page - Analog Devices

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AD5672R/AD5676R
Data Sheet
Rev. B | Page 8 of 34
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V, and VREFIN = 2.5 V. All specifications −40°C to +125°C, unless otherwise noted. Maximum
SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ VDD. Guaranteed by design and characterization; not production tested.
Table 5.
1.8 V ≤ VLOGIC < 2.7 V
2.7 V ≤ VLOGIC ≤ 5.5 V
Parameter
Min
Max
Min
Max
Unit
Description
t1
20
20
ns
SCLK Cycle Time
t2
4
1.7
ns
SCLK High Time
t3
4.5
4.3
ns
SCLK Low Time
t4
15.1
10.1
ns
SYNC to SCLK Falling Edge Setup Time
t5
0.8
0.8
ns
Data Setup Time
t6
0.1
−0.8
ns
Data Hold Time
t7
0.95
1.25
ns
SCLK Falling Edge to SYNC Rising Edge
t8
9.65
6.75
ns
Minimum SYNC High Time (Single, Combined, or All Channel Update)
t9
4.75
9.7
ns
SYNC Falling Edge to SCLK Fall Ignore
t10
4.85
5.45
ns
LDAC Pulse Width Low
t11
41.25
25
ns
SCLK Falling Edge to LDAC Rising Edge
t12
26.35
20.3
ns
SCLK Falling Edge to LDAC Falling Edge
t13
4.8
6.2
ns
RESET Minimum Pulse Width Low
t14
132
80
ns
RESET Pulse Activation Time
5.15
5.18
μs
Power-Up Time1
1
Time to exit power-down to normal mode of AD5672R/AD5676R operation, 32nd clock edge to 90% of DAC midscale value, with output unloaded.
t4
t3
SCLK
SYNC
SDI
t1
t2
t5
t6
t7
t8
DB23
t9
t10
t11
LDAC1
LDAC2
t12
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
RESET
t13
t14
VOUT
DB0
Figure 2. Serial Write Operation


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