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SI53106 Arkusz danych(PDF) 9 Page - Silicon Laboratories |
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SI53106 Arkusz danych(HTML) 9 Page - Silicon Laboratories |
9 / 34 page Si53106 Rev. 1.2 9 Table 6. DIF 0.7 V AC Timing Characteristics (Non-Spread Spectrum Mode)1 Parameter Symbol CLK 100 MHz, 133 MHz Unit Notes Min Typ Max Clock Stabilization Time TSTAB — 1.5 1.8 ms 2 Long Term Accuracy LACC — — 100 ppm 3,4,5 Absolute Host CLK Period (100MHz) TABS 9.94900 — 10.05100 ns 3,4,6 Absolute Host CLK Period (133MHz) TABS 7.44925 — 7.55075 ns 3,4,6 Edge Rate Edge_rate 1.0 — 4.0 V/ns 3,4,7 Rise Time Variation ∆ TRISE — — 125 ps 3,8,9 Fall Time Variation ∆ TFALL — — 125 ps 3,8,9 Rise/Fall Matching TRISE_MAT/ TFALL_MAT —— 20 % 3,8,10,11 Voltage High (typ 0.7 V) VHIGH 660 — 850 mV 3,8,12 Voltage Low (typ 0.7 V) VLOW –150 — 150 mV 3,8,13 Maximum Voltage VMAX —— 1150 mV 8 Absolute Crossing Point Voltages VoxABS 250 — 550 mV 3,8,14,15, 16 Total Variation of VCROSS Over All Edges Total ∆ Vox — — 140 mV 3,8,18 Duty Cycle DC 45 — 55 % 3,4 Maximum Voltage (Overshoot) Vovs —— VHigh + 0.3 V 3,8,19 Maximum Voltage (Undershoot) Vuds —— VLow – 0.3 V 3,8,20 |
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