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SI53108 Arkusz danych(PDF) 6 Page - Silicon Laboratories

Numer części SI53108
Szczegółowy opis  DB800ZL 8-OUTPUT PCIE GEN 3 BUFFER/ZERO DELAY BUFFER
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Producent  SILABS [Silicon Laboratories]
Strona internetowa  http://www.silabs.com
Logo SILABS - Silicon Laboratories

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Si53108
6
Rev. 1.2
Table 5. Output Relational Timing Parameters
TA = –40 to 85 °C; supply voltage VDD =3.3 V ±5%
Parameter
Test Condition
Min
TYP
Max
Unit
Notes
CLK_IN, DIF[x:0]
Input-to-Output Delay in PLL Mode
Nominal Value
–100
20
100
ps
1,2,4,5
CLK_IN, DIF[x:0]
Input-to-Output Delay in Bypass Mode
Nominal Value
2.5
3.3
4.5
ns
2,3,5
CLK_IN, DIF[x:0]
Input-to-Output Delay Variation in PLL
mode (over voltage and temperature)
Nominal Value
–100
39
100
ps
2,3,5
CLK_IN, DIF[x:0]
Input-to-Output Delay Variation in Bypass
Mode (over voltage and temperature)
Nominal Value
–250
250
ps
2,3,5
CLK_IN, DIF[7:0]
Output-to-Output Skew across all 12 out-
puts (Common to Bypass and PLL mode)
0
25
50
ps
1,2,3,5
Notes:
1.
Measured into fixed 2 pF load cap. Input-to-output skew is measured at the first output edge following the
corresponding input.
2.
Measured from differential cross-point to differential cross-point.
3.
All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created
by it.
4.
This parameter is deterministic for a given device.
5.
Measured with scope averaging on to find mean value
Table 6. PLL Bandwidth and Peaking
TA = –40 to 85 °C; supply voltage VDD =3.3 V ±5%
Parameter
Test Condition
Min
TYP
Max
Unit
Notes
PLL Jitter Peaking
HBW_BYPASS_LBW = 0
0.4
2.0
dB
2
PLL Jitter Peaking
HBW_BYPASS_LBW =1
0.1
2.0
dB
2
PLL Bandwidth
HBW_BYPASS_LBW =1
2
3
4
MHz
1
PLL Bandwidth
HBW_BYPASS_LBW = 0
0.7
1
1.4
MHz
1
Notes:
1.
Measured at 3 db down or half power point.
2.
Measured as maximum pass band gain. At frequencies with the loop BW, highest point of magnification is call PLL
jitter peaking.


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