Si53304

Rev. 1.0

9

Figure 1. Differential Measurement Method Using a Balun

Table 12. Additive Jitter, Single-Ended Clock Input

Input1,2

Output

Additive Jitter

(fs rms, 12 kHz to

20 MHz)3

Freq

(MHz)

Clock Format

Amplitude

(single-ended,

peak to peak)

SE 20%-80%

Slew Rate

(V/ns)

Clock Format

Typ

Max

3.3

200

Single-ended

1.70

1

LVCMOS4

120

160

3.3

156.25

Single-ended

2.18

1

LVPECL

160

185

3.3

156.25

Single-ended

2.18

1

LVDS

150

200

3.3

156.25

Single-ended

2.18

1

LVCMOS4

130

180

2.5

200

Single-ended

1.70

1

LVCMOS5

120

160

2.5

156.25

Single-ended

2.18

1

LVPECL

145

185

2.5

156.25

Single-ended

2.18

1

LVDS

145

195

2.5

156.25

Single-ended

2.18

1

LVCMOS5

140

180

Notes:

1.

For best additive jitter results, use the fastest slew rate possible. See “AN766: Understanding and Optimizing Clock

Buffer’s Additive Jitter Performance” for more information.

2.

DC-coupled single-ended inputs.

3.

Measured differentially using a balun at the phase noise analyzer input. See Figure 1.

4.

Drive Strength: 12 mA, 3.3 V (SFOUT = 11). LVCMOS jitter is measured single-ended.

5.

Drive Strength: 9 mA, 2.5 V (SFOUT = 11). LVCMOS jitter is measured single-ended.

PSPL 5310A

CLKx

/CLKx

50

50

Balun

50ohm

AG E5052 Phase Noise

Analyzer

Si533xx

DUT

PSPL 5310A

CLK SYNTH

SMA103A

Balun