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CDCL1810RGZT Arkusz danych(PDF) 1 Page - Texas Instruments

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Numer części CDCL1810RGZT
Szczegółowy opis  Output, High-Performance Clock Distributor
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CDCL1810RGZT Arkusz danych(HTML) 1 Page - Texas Instruments

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SDA/SCL
Differential
LVDSInput
Upto650MHz
5Differential
CMLOutputs
Upto650MHz
5Differential
CMLOutputs
Upto650MHz
DIVIDER
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CDCL1810
SLLS781D – FEBRUARY 2007 – REVISED NOVEMBER 2014
CDCL1810 1.8-V, 10 Output, High-Performance Clock Distributor
1 Features
3 Description
The
CDCL1810
is
a
high-performance
clock
1
Single 1.8-V Supply
distributor. The programmable dividers, P0 and P1,
High-Performance Clock Distributor with 10
give a high flexibility to the ratio of the output
Outputs
frequency to the input frequency: FOUT = FIN/P,
Low Input-to-Output Additive Jitter:
where: P (P0,P1) = 1, 2, 4, 5, 8, 10, 16, 20, 32, 40,
80.
as Low as 10fs RMS
Output Group Phase Adjustment
The CDCL1810 supports one differential LVDS clock
input and a total of 10 differential CML outputs. The
Low-Voltage Differential Signaling (LVDS) Input,
CML outputs are compatible with LVDS receivers if
100-
Ω Differential On-Chip Termination, up to 650
they are ac-coupled.
MHz Frequency
With careful observation of the input voltage swing
Differential Current Mode Logic (CML) Outputs,
and common-mode voltage limits, the CDCL1810 can
50-
Ω Single-Ended On-Chip Termination, up to
support a single-ended clock input as outlined in Pin
650 MHz Frequency
Configuration and Functions.
Two Groups of Five Outputs Each with
All device settings are programmable through the
Independent Frequency Division Ratios
SDA/SCL,
serial
two-wire
interface.
The
serial
Output Frequency Derived with Divide Ratios of 1,
interface is 1.8V tolerant only.
2, 4, 5, 8, 10, 16, 20, 32, 40, and 80
The phase of one output group relative to the other
Meets ANSI TIA/EIA-644-A-2001 LVDS Standard
can be adjusted through the SDA/SCL interface. For
Requirements
post-divide ratios (P0, P1) that are multiples of 5, the
Power Consumption: 410 mW Typical
total number of phase adjustment steps (n) equals
Output Enable Control for Each Output and
the divide-ratio divided by 5. For post-divide ratios
Automatic Output Synchronization
(P0, P1) that are not multiples of 5, the total number
of steps (n) is the same as the post-divide ratio. The
SDA/SCL Device Management Interface
phase adjustment step (
ΔΦ) in time units is given as:
48-pin VQFN (RGZ) Package
ΔΦ = 1/(n × FOUT), where FOUT is the respective
Industrial Temperature Range: –40°C to +85°C
output frequency.
The device operates in a 1.8-V supply environment
2 Applications
and is characterized for operation from –40°C to
Distribution for High-Speed SERDES
+85°C. The CDCL1810 is available in a 48-pin VQFN
(RGZ) package.
Distribution of SERDES Reference Clocks for
1G/10G Ethernet, 1X/2X/4X/10X Fibre Channel,
Device Information(1)
PCI Express, Serial ATA, SONET, CPRI, OBSAI,
PART NUMBER
PACKAGE
BODY SIZE (NOM)
etc.
CDCL1810
VQFN (48)
7.00 mm × 7.00 mm
Up to 1-to-10 Clock Buffering and Fan-out
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Functional Block Diagram
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.


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