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CDCLVP1204RGTR Arkusz danych(PDF) 1 Page - Texas Instruments |
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CDCLVP1204RGTR Arkusz danych(HTML) 1 Page - Texas Instruments |
1 / 32 page LVPECL 4 4 Reference Generator GND OUTP[3...0] OUTN[3...0] V CC V AC_REF INP0 INN0 INP1 INN1 IN_SEL 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 2.0 1.8 Frequency (GHz) 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 V = 3.0 V T = 40 C to +85 C V = 1 V V = Min CC A ICM IN,DIFF,PP - ° ° Product Folder Sample & Buy Technical Documents Tools & Software Support & Community Reference Design CDCLVP1204 SCAS880F – AUGUST 2009 – REVISED SEPTEMBER 2015 CDCLVP1204 Four LVPECL Output, High-Performance Clock Buffer 1 Features 3 Description The CDCLVP1204 is a highly versatile, low additive 1 • 2:4 Differential Buffer jitter buffer that can generate four copies of LVPECL • Selectable Clock Inputs Through Control Terminal clock outputs from one of two selectable LVPECL, • Universal Inputs Accept LVPECL, LVDS, and LVDS, or LVCMOS inputs for a variety of LVCMOS/LVTTL communication applications. It has a maximum clock frequency up to 2 GHz. The CDCLVP1204 features • Four LVPECL Outputs an on-chip multiplexer (MUX) for selecting one of two • Maximum Clock Frequency: 2 GHz inputs that can be easily configured solely through a • Maximum Core Current Consumption: 45 mA control terminal. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to • Very Low Additive Jitter: <100 fs, RMS in 10-kHz 20 MHz, and overall output skew is as low as 15 ps, to 20-MHz Offset Range: making the device a perfect choice for use in – 57 fs, RMS (typical) at 122.88 MHz demanding applications. – 48 fs, RMS (typical) at 156.25 MHz The CDCLVP1204 clock buffer distributes one of two – 30 fs, RMS (typical) at 312.5 MHz selectable clock inputs (IN0, IN1) to four pairs of • 2.375-V to 3.6-V Device Power Supply differential LVPECL clock outputs (OUT0, OUT3) with minimum skew for clock distribution. The • Maximum Propagation Delay: 450 ps CDCLVP1204 can accept two clock sources into an • Maximum Output Skew: 15 ps input multiplexer. The inputs can be LVPECL, LVDS, • LVPECL Reference Voltage, VAC_REF, Available or LVCMOS/LVTTL. for Capacitive-Coupled Inputs The CDCLVP1204 is specifically designed for driving • Industrial Temperature Range: –40°C to +85°C 50- Ω transmission lines. When driving the inputs in • Supports 105°C PCB Temperature (Measured at single-ended mode, the LVPECL bias voltage Thermal Pad) (VAC_REF) must be applied to the unused negative input terminal. However, for high-speed performance • ESD Protection Exceeds 2 kV (HBM) up to 2 GHz, differential mode is strongly recommended. 2 Applications The CDCLVP1204 is characterized for operation from • Wireless Communications –40°C to +85°C. • Telecommunications/Networking • Medical Imaging Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) • Test and Measurement Equipment CDCLVP1204 QFN (16) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic Differential Output Peak-to-Peak Voltage vs. Frequency 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. |
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