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CDCM7005 Arkusz danych(PDF) 6 Page - Texas Instruments |
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CDCM7005 Arkusz danych(HTML) 6 Page - Texas Instruments |
6 / 52 page CDCM7005 SCAS793F – JUNE 2005 – REVISED JULY 2015 www.ti.com Pin Functions (continued) PIN I/O DESCRIPTION NAME BGA QFN This LVCMOS input can be programmed (SPI) to act as HOLD or RESET. RESET is the default function. This pin is low active and can be activated external or via the corresponding bit in the SPI register. In case of RESET, the charge pump (CP) is switched to 3-state and all counters (N, M, P) are reset to zero (the initial divider settings are maintained in SPI registers). The LVPECL outputs are static low and high respectively and the LVCMOS outputs are all low or high if inverted. RESET is not edge triggered and should have a pulse duration of at least 5 ns. RESET H8 14 I In case of HOLD, the CP is switched in to 3-state mode only. After HOLD is released and with the next valid reference clock cycle the charge pump is switched back in to normal operation (CP stays in 3-state as long as no reference clock is valid). During HOLD, the P divider and all outputs Yx are at normal operation. This mode allows an external control of the frequency hold-over mode. The input has an internal 150-k Ω pullup resistor. LVCMOS input for the secondary reference clock, with an internal 150-k Ω pullup SEC_REF B1 37 I resistor and input hysteresis. This output can be programmed (SPI) to provide either the STATUS_REF or PRI_SEC_CLK information. This pin is set high if one of the STATUS conditions is valid. STATUS_REF is the default setting. In case of STATUS_REF, the LVCMOS output provides the Status of the STATUS_REF or C8 23 O Reference Clock. If a reference clock with a frequency above 2 MHz is provided to PRI_REF or SEC_REF STATUS_REF will be set high. In case of PRI_SEC_CLK, the LVCMOS output indicates whether the primary clock [high] or the secondary clock [low] is selected. This LVCMOS output can be programmed (SPI) to provide either the STATUS_VCXO information or serve as current path for the charge pump (CP). STATUS_VCXO is the default setting. In case of STATUS_VCXO, the LVCMOS output provides the status of the VCXO STATUS_VCXO D8 22 O input (frequencies above 2 MHz are interpreted as valid clock; active high). In case of I_REF_CP, it provides the current path for the external reference resistor (12 k Ω ±1%) to support an accurate charge pump current, optional. Do not use any capacitor across this resistor to prevent noise coupling via this node. If the internal 12 k Ω is selected (default setting), this pin can be left open. Bias voltage output to be used to bias unused complementary input VCXO_IN for VBB C1 40 O single ended signals. The output of VBB is VCC – 1.3 V. The output current is limited to about 1.5 mA. D7, E3, 2, 5, 6, E4, E5, 9, 10, E6, E7, 13, 15, 3.3-V supply. VCC and AVCC should always have the same supply voltage. It is VCC E8, F7, 18, 19, Power recommended that AVCC use its own supply filter. G2, G3, 20, 21, G4, G5, 41, 44, G6, G7 45; 48 This is the charge pump power supply pin used to have the same supply as the VCC_CP A3 33 Power external VCO. It can be set from 2.3 V to 3.6 V. VCXO_IN E1 43 I VCXO LVPECL input VCXO_IN D1 42 I Complementary VCXO LVPECL input Y0A:Y0B F1, G1, 46, 47, The outputs of the CDCM7005 are user definable and can be any combination of Y1A:Y1B H2, H3, 3, 4, up to five LVPECL outputs or up to 10 LVCMOS outputs. The outputs are Y2A:Y2B H4, H5, 7, 8, O selectable via SPI (Word 1, Bit 2-6). The power-up setting is all outputs are Y3A:Y3B H6, H7, 11,12, LVPECL. Y4A:Y4B G8, F8 16, 17 6 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: CDCM7005 |
Podobny numer części - CDCM7005_15 |
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Podobny opis - CDCM7005_15 |
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