Zakładka z wyszukiwarką danych komponentów
  Polish  ▼
ALLDATASHEET.PL

X  

CDCM7005 Arkusz danych(PDF) 6 Page - Texas Instruments

Numer części CDCM7005
Szczegółowy opis  3.3-V High Performance Clock Synchronizer and Jitter Cleaner
Download  52 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Producent  TI1 [Texas Instruments]
Strona internetowa  http://www.ti.com
Logo TI1 - Texas Instruments

CDCM7005 Arkusz danych(HTML) 6 Page - Texas Instruments

Back Button CDCM7005_15 Datasheet HTML 2Page - Texas Instruments CDCM7005_15 Datasheet HTML 3Page - Texas Instruments CDCM7005_15 Datasheet HTML 4Page - Texas Instruments CDCM7005_15 Datasheet HTML 5Page - Texas Instruments CDCM7005_15 Datasheet HTML 6Page - Texas Instruments CDCM7005_15 Datasheet HTML 7Page - Texas Instruments CDCM7005_15 Datasheet HTML 8Page - Texas Instruments CDCM7005_15 Datasheet HTML 9Page - Texas Instruments CDCM7005_15 Datasheet HTML 10Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 6 / 52 page
background image
CDCM7005
SCAS793F – JUNE 2005 – REVISED JULY 2015
www.ti.com
Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
BGA
QFN
This LVCMOS input can be programmed (SPI) to act as HOLD or RESET. RESET
is the default function. This pin is low active and can be activated external or via
the corresponding bit in the SPI register. In case of RESET, the charge pump (CP)
is switched to 3-state and all counters (N, M, P) are reset to zero (the initial divider
settings are maintained in SPI registers). The LVPECL outputs are static low and
high respectively and the LVCMOS outputs are all low or high if inverted. RESET
is not edge triggered and should have a pulse duration of at least 5 ns.
RESET
H8
14
I
In case of HOLD, the CP is switched in to 3-state mode only. After HOLD is
released and with the next valid reference clock cycle the charge pump is
switched back in to normal operation (CP stays in 3-state as long as no reference
clock is valid). During HOLD, the P divider and all outputs Yx are at normal
operation. This mode allows an external control of the frequency hold-over mode.
The input has an internal 150-k
Ω pullup resistor.
LVCMOS input for the secondary reference clock, with an internal 150-k
Ω pullup
SEC_REF
B1
37
I
resistor and input hysteresis.
This output can be programmed (SPI) to provide either the STATUS_REF or
PRI_SEC_CLK information. This pin is set high if one of the STATUS conditions is
valid. STATUS_REF is the default setting.
In case of STATUS_REF, the LVCMOS output provides the Status of the
STATUS_REF or
C8
23
O
Reference Clock. If a reference clock with a frequency above 2 MHz is provided to
PRI_REF or SEC_REF STATUS_REF will be set high.
In case of PRI_SEC_CLK, the LVCMOS output indicates whether the primary
clock [high] or the secondary clock [low] is selected.
This LVCMOS output can be programmed (SPI) to provide either the
STATUS_VCXO information or serve as current path for the charge pump (CP).
STATUS_VCXO is the default setting.
In case of STATUS_VCXO, the LVCMOS output provides the status of the VCXO
STATUS_VCXO
D8
22
O
input (frequencies above 2 MHz are interpreted as valid clock; active high).
In case of I_REF_CP, it provides the current path for the external reference
resistor (12 k
Ω ±1%) to support an accurate charge pump current, optional. Do not
use any capacitor across this resistor to prevent noise coupling via this node. If
the internal 12 k
Ω is selected (default setting), this pin can be left open.
Bias voltage output to be used to bias unused complementary input VCXO_IN for
VBB
C1
40
O
single ended signals. The output of VBB is VCC – 1.3 V. The output current is
limited to about 1.5 mA.
D7, E3,
2, 5, 6,
E4, E5,
9, 10,
E6, E7,
13, 15,
3.3-V supply. VCC and AVCC should always have the same supply voltage. It is
VCC
E8, F7,
18, 19,
Power
recommended that AVCC use its own supply filter.
G2, G3,
20, 21,
G4, G5,
41, 44,
G6, G7
45; 48
This is the charge pump power supply pin used to have the same supply as the
VCC_CP
A3
33
Power
external VCO. It can be set from 2.3 V to 3.6 V.
VCXO_IN
E1
43
I
VCXO LVPECL input
VCXO_IN
D1
42
I
Complementary VCXO LVPECL input
Y0A:Y0B
F1, G1,
46, 47,
The outputs of the CDCM7005 are user definable and can be any combination of
Y1A:Y1B
H2, H3,
3, 4,
up to five LVPECL outputs or up to 10 LVCMOS outputs. The outputs are
Y2A:Y2B
H4, H5,
7, 8,
O
selectable via SPI (Word 1, Bit 2-6). The power-up setting is all outputs are
Y3A:Y3B
H6, H7,
11,12,
LVPECL.
Y4A:Y4B
G8, F8
16, 17
6
Submit Documentation Feedback
Copyright © 2005–2015, Texas Instruments Incorporated
Product Folder Links: CDCM7005


Podobny numer części - CDCM7005_15

ProducentNumer częściArkusz danychSzczegółowy opis
logo
Texas Instruments
CDCM7005 TI-CDCM7005_13 Datasheet
1Mb / 45P
[Old version datasheet]   3.3-V HIGH PERFORMANCE CLOCK SYNCHRONIZER AND JITTER CLEANER
More results

Podobny opis - CDCM7005_15

ProducentNumer częściArkusz danychSzczegółowy opis
logo
Texas Instruments
CDCM7005 TI-CDCM7005 Datasheet
1Mb / 40P
[Old version datasheet]   3.3-V HIGH PERFORMANCE CLOCK SYNCHRONIZER AND JITTER CLEANER
CDCM7005 TI-CDCM7005_13 Datasheet
1Mb / 45P
[Old version datasheet]   3.3-V HIGH PERFORMANCE CLOCK SYNCHRONIZER AND JITTER CLEANER
CDCM7005-SP TI1-CDCM7005-SP Datasheet
570Kb / 41P
[Old version datasheet]   3.3-V HIGH PERFORMANCE RAD-TOLERANT CLASS V, CLOCK SYNCHRONIZER AND JITTER CLEANER
CDC7005RGZT TI-CDC7005RGZT Datasheet
1Mb / 34P
[Old version datasheet]   3.3-V HIGH PERFORMANCE CLOCK SYNTHSIZER AND JITTER CLEANER
CDC7005 TI-CDC7005 Datasheet
397Kb / 29P
[Old version datasheet]   3.3-V HIGH PERFORMANCE CLOCK SYNTHESIZER AND JITTER CLEANER
CDCM7005-SP TI1-CDCM7005-SP_16 Datasheet
1Mb / 49P
[Old version datasheet]   CDCM7005-SP 3.3-V High Performance Rad-Tolerant Class V, Clock Synchronizer and Jitter Cleaner
CDCE72010 TI-CDCE72010 Datasheet
1Mb / 70P
[Old version datasheet]   Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor
CDCE72010 TI-CDCE72010_09 Datasheet
1Mb / 73P
[Old version datasheet]   Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor
logo
Analog Devices
AD9523 AD-AD9523 Datasheet
1,011Kb / 60P
   Jitter Cleaner and Clock Generator
AD9524 AD-AD9524_15 Datasheet
973Kb / 56P
   Jitter Cleaner and Clock Generator
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52


Arkusz danych Pobierz

Go To PDF Page


Link URL




Polityka prywatności
ALLDATASHEET.PL
Czy Alldatasheet okazała się pomocna?  [ DONATE ] 

O Alldatasheet   |   Reklama   |   Kontakt   |   Polityka prywatności   |   Linki   |   Lista producentów
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com