AN349

10

Rev. 0.1

Figure 5. Powerdown Timing

3.2.2. XOSCEN-Crystal Oscillator Enable (Not available on Si4708/09)

The internal oscillator is not available on the Si4708/09. The Si4708/09-B requires a 32.768 kHz reference clock to

the RCLK pin. Refer to the Si4708/09 datasheet for more information.

3.2.3. AHIZEN (07h.14)—Audio High-Z Enable

For information on audio high-Z enable, refer to Section 3.2.3 of “AN230: Si4700/01/02/03 Programming Guide."

3.2.4. GPIO1-General Purpose I/O 1 (Not available on Si4708/09)

General purpose I/O 1 is not available on the Si4708/09.

3.2.5. GPO (04h.3:2)/RDSIEN (04h.15)/STCIEN (04h.14)—General Purpose I/O, Interrupts

GPO can be programmed to four different states as shown in Table 5. When programmed as an interrupt, the

device will generate interrupts based on the settings of RDSIEN and STCIEN. If RDSIEN is set a 5 ms interrupt

pulse will be generated when RDS data is available. If STCIEN is set a 5 ms interrupt pulse will be generated upon

completion of a SEEK or TUNE command. If both interrupts are enabled, the first interrupt after a SEEK or TUNE

will be the STC interrupt. Subsequent interrupts will be RDS interrupts. This pin can also be used as a general

purpose output or left unused. RDS is only available on the Si4709.

Table 4. Powerdown Sequence

Write address 07h (optional for LOUT and ROUT Hi-Z).

Example: Write data 7C04h.

Write address 04h (This step is required for the Si4708/09 to reduce powerdown mode current).

read.

Example: Write data 002Ah.

Write address 02h (required).

ENABLE and DISABLE bits low. Setting the ENABLE bit directly to 0 will cause the device to partially

powerdown.

Example: Write data 0041h.

WR02

1.5 ms max

ENABLE = 1

DISABLE = 1

RD02

ENABLE = 0

DISABLE = 0

Optional

Required