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SI21662-B22 Arkusz danych(PDF) 2 Page - Silicon Laboratories |
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SI21662-B22 Arkusz danych(HTML) 2 Page - Silicon Laboratories |
2 / 2 page Dual Digital Demodulators Copyright © 2015 by Silicon Laboratories 10.29.2015 Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. Si21662-B22 Dual DVB-S/S2 Digital TV Demodulator Selected Electrical Specifications (TA = –10 to 70 °C). Parameter Test Condition Min Typ Max Unit General Input clock reference 4 — 30 MHz Supported XTAL frequency 16 — 30 MHz Total power consumption for each demodulator DVB-S1 — 240 — mW DVB-S22 — 465 — mW Thermal resistance (JA) 4 layer PCB — 42 — °C/W Power Supplies VDD_VCORE 1.14 1.20 1.30 V VDD_VANA 3.00 3.30 3.60 V VDD_VIO 3.00 3.30 3.60 V Notes: 1. Test conditions: 30 MBaud, CR=7/8, parallel TS (at QEF: BER = 2. 10–4). 2. Test conditions: 32 MBaud, 3/5 Code Rate, 8PSK, pilots On, parallel TS, C/N at picture failure. Pin Assignments Selection Guide Part # Description Si21662-B22-GM/R Dual Digital TV Demodulator for DVB-S/S2, 8x8 mm QFN-68 Si21662B (GND_PAD) QFN-68 8x8mm 66 65 64 63 67 68 3 4 5 6 7 8 9 10 11 12 2 1 13 14 49 50 51 48 47 43 44 45 46 42 41 40 39 38 15 16 17 26 27 28 29 25 20 21 22 23 24 19 18 34 33 30 31 32 35 36 37 TS_CLK_A TS_CLK_B TS_DATA[0]_A/TS_SER_A TS_DATA[0]_B/TS_SER_B TS_DATA[1]_A TS_DATA[1]_B TS_DATA[2]_A TS_DATA[2]_B TS_DATA[3]_A TS_DATA[3]_B TS_DATA[4]_A TS_DATA[4]_B VDD_CORE VDD_CORE GND VDD_VIO TS_DATA[5]_A 60 59 58 57 61 62 54 53 52 55 56 VDD_CORE VDD_CORE GND SCL_MAST SDA_MAST CLK_IN_OUT NC NC NC NC S_ADC_QN_B S_ADC_QP_B S_ADC_IN_B S_ADC_IP_B S_ADC_QN_A S_ADC_QP_A S_ADC_IN_A |
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